Datasheet

Rev.6.00 Oct.28.2004 page 6 of 1016
REJ09B0138-0600H
1.2 Block Diagram
Figure 1-1 shows an internal block diagram of the H8S/2357 Group.
PE
7
/D
7
PE
6
/D
6
PE
5
/D
5
PE
4
/D
4
PE
3
/D
3
PE
2
/D
2
PE
1
/D
1
PE
0
/D
0
PD
7
/D
15
PD
6
/D
14
PD
5
/D
13
PD
4
/D
12
PD
3
/D
11
PD
2
/D
10
PD
1
/D
9
PD
0
/D
8
Port D
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Port
A
PA
7
/A
23
/IRQ7
PA
6
/A
22
/IRQ6
PA
5
/A
21
/IRQ5
PA
4
/A
20
/IRQ4
PA
3
/A
19
PA
2
/A
18
PA
1
/A
17
PA
0
/A
16
PB
7
/A
15
PB
6
/A
14
PB
5
/A
13
PB
4
/A
12
PB
3
/A
11
PB
2
/A
10
PB
1
/A
9
PB
0
/A
8
PC
7
/A
7
PC
6
/A
6
PC
5
/A
5
PC
4
/A
4
PC
3
/A
3
PC
2
/A
2
PC
1
/A
1
PC
0
/A
0
P3
5
/SCK1
P3
4
/SCK0
P3
3
/RxD1
P3
2
/RxD0
P3
1
/TxD1
P3
0
/TxD0
P5
0
/TxD2
P5
1
/RxD2
P5
2
/SCK2
P5
3
/ADTRG
P4
7
/AN7/DA1
P4
6
/AN6/DA0
P4
5
/AN5
P4
4
/AN4
P4
3
/AN3
P4
2
/AN2
P4
1
/AN1
P4
0
/AN0
V
ref
AV
CC
AV
SS
P2
0
/PO0/TIOCA3
P2
1
/PO1/TIOCB3
P2
2
/PO2/TIOCC3/TMRI0
P2
3
/PO3/TIOCD3/TMCI0
P2
4
/PO4/TIOCA4/TMRI1
P2
5
/PO5/TIOCB4/TMCI1
P2
6
/PO6/TIOCA5/TMO0
P2
7
/PO7/TIOCB5/TMO1
P1
0
/PO8/TIOCA0/DACK0
P1
1
/PO9/TIOCB0/DACK1
P1
2
/PO10/TIOCC0/TCLKA
P1
3
/PO11/TIOCD0/TCLKB
P1
4
/PO12/TIOCA1
P1
5
/PO13/TIOCB1/TCLKC
P1
6
/PO14/TIOCA2
P1
7
/PO15/TIOCB2/TCLKD
P6
7
/CS7/IRQ3
P6
6
/CS6/IRQ2
P6
5
/IRQ1
P6
4
/IRQ0
P6
3
/TEND1
P6
2
/DREQ1
P6
1
/TEND0/CS5
P6
0
/DREQ0/CS4
PG
4
/CS0
PG
3
/CS1
PG
2
/CS2
PG
1
/CS3
PG
0
/CAS
PF
7
/ø
PF
6
/AS
PF
5
/RD
PF
4
/HWR
PF
3
/LWR
PF
2
/LCAS/WAIT/BREQO
PF
1
/BACK
PF
0
/BREQ
Notes: 1.
2.
This pin functions as the WDTOVF pin function in ZTAT, and masked ROM products, and in the H8S/2352.
In the H8S/2357F-ZTAT, the WDTOVF pin function is not available, because this pin is used as the FWE
pin.
In the H8S/2398, H8S/2394, H8S/2392, and H8S/2390, the WDTOVF pin function is not available,
because this pin is used as the V
CL
pin.
In ROMless version, ROM is not supported.
Clock pulse
generator
ROM
*
2
RAM
WDT
TPU
SCI
PPG
MD
2
MD
1
MD
0
EXTAL
XTAL
STBY
RES
WDTOVF (FWE, V
CL
)
*
1
NMI
Bus controller
H8S/2000 CPU
DTC
Interrupt controller
Port E
DMAC
Internal data bus Internal address bus
Port
B
Port
C
Port
3
Port
5
Port 4Port 2Port 1
Port
6
Port
G
Port
F
Peripheral data bus Peripheral address bus
8-bit timer
D/A converter
A/D converter
Figure 1-1 Block Diagram