Datasheet

Rev.6.00 Oct.28.2004 page 329 of 1016
REJ09B0138-0600H
Port F Data Register (PFDR)
Bit:76543210
PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF
7
to PF
0
).
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port F Register (PORTF)
Bit:76543210
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
Initial value : —* —* —* —* —* —* —* —*
R/W:RRRRRRRR
Note: * Determined by state of pins PF
7
to PF
0
.
PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port F pins (PF
7
to PF
0
) must
always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while
PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and
PFDR are initialized. PORTF retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.