Datasheet

Rev.6.00 Oct.28.2004 page 323 of 1016
REJ09B0138-0600H
9.12.2 Register Configuration
Table 9-21 shows the port E register configuration.
Table 9-21 Port E Registers
Name Abbreviation R/W Initial Value Address*
1
Port E data direction register PEDDR W H'00 H'FEBD
Port E data register PEDR R/W H'00 H'FF6D
Port E register PORTE R Undefined H'FF5D
Port E MOS pull-up control register*
2
PEPCR R/W H'00 H'FF74
Notes: 1. Lower 16 bits of the address.
2. PEPCR settings are prohibited in the ROMless version.
Port E Data Direction Register (PEDDR)
Bit:76543210
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
Initial value : 0 0 0 0 0 0 0 0
R/W:WWWWWWWW
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR
cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7*
Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin
an input port.
Note: * Modes 6 and 7 are provided in the on-chip ROM version only.
• Modes 4 to 6*
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the
corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is
designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller.
Port E Data Register (PEDR)
Bit:76543210
PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE
7
to PE
0
).