Datasheet

Rev.6.00 Oct.28.2004 page 318 of 1016
REJ09B0138-0600H
9.11.2 Register Configuration (On-Chip ROM Version Only)
Table 9-19 shows the port D register configuration.
Table 9-19 Port D Registers
Name Abbreviation R/W Initial Value Address *
Port D data direction register PDDDR W H'00 H'FEBC
Port D data register PDDR R/W H'00 H'FF6C
Port D register PORTD R Undefined H'FF5C
Port D MOS pull-up control register PDPCR R/W H'00 H'FF73
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR) (On-Chip ROM Version Only)
Bit:76543210
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value : 0 0 0 0 0 0 0 0
R/W:WWWWWWWW
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR
cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin
an input port.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O.
Port D Data Register (PDDR) (On-Chip ROM Version Only)
Bit:76543210
PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD
7
to PD
0
).
PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.