Datasheet

Rev.6.00 Oct.28.2004 page 313 of 1016
REJ09B0138-0600H
9.10.2 Register Configuration (On-Chip ROM Version Only)
Table 9-17 shows the port C register configuration.
Table 9-17 Port C Registers
Name Abbreviation R/W Initial Value Address *
Port C data direction register PCDDR W H'00 H'FEBB
Port C data register PCDR R/W H'00 H'FF6B
Port C register PORTC R Undefined H'FF5B
Port C MOS pull-up control register PCPCR R/W H'00 H'FF72
Note: * Lower 16 bits of the address.
Port C Data Direction Register (PCDDR) (On-Chip ROM Version Only)
Bit:76543210
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value : 0 0 0 0 0 0 0 0
R/W:WWWWWWWW
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR
cannot be read; if it is, an undefined value will be read.
PCDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their
output state or become high-impedance when a transition is made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
• Mode 7
Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin
an input port.
• Mode 6
Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the
pin an input port.
• Modes 4 and 5
The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.
Port C Data Register (PCDR) (On-Chip ROM Version Only)
Bit:76543210
PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC
7
to PC
0
).
PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.