Datasheet

Rev.6.00 Oct.28.2004 page 308 of 1016
REJ09B0138-0600H
9.9.2 Register Configuration (On-Chip ROM Version Only)
Table 9-15 shows the port B register configuration.
Table 9-15 Port B Registers
Name Abbreviation R/W Initial Value Address *
Port B data direction register PBDDR W H'00 H'FEBA
Port B data register PBDR R/W H'00 H'FF6A
Port B register PORTB R Undefined H'FF5A
Port B MOS pull-up control register PBPCR R/W H'00 H'FF71
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR) (On-Chip ROM Version Only)
Bit:76543210
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value : 0 0 0 0 0 0 0 0
R/W:WWWWWWWW
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR
cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their
output state or become high-impedance when a transition is made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin
an input port.
Mode 6
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the
pin an input port.
Modes 4 and 5
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Port B Data Register (PBDR) (On-Chip ROM Version Only)
Bit:76543210
PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB
7
to PB
0
). PBDR is initialized to
H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software
standby mode.