Datasheet

Rev.6.00 Oct.28.2004 page 276 of 1016
REJ09B0138-0600H
Pin Selection Method and Pin Functions
P1
2
/PO10/TIOCC0/
TCLKA
The pin function is switched as shown below according to the combination of
the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in
TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to
TCR5, bit NDER10 in NDERH, and bit P12DDR.
TPU Channel
0 Setting Table Below (1) Table Below (2)
P12DDR — 0 1 1
NDER10 — — 0 1
Pin function TIOCC0 output P1
2
input
P1
2
output
PO10
output
TIOCC0 input *
1
TCLKA input *
2
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =
B'10××.
2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to
TPSC0 = B'100;
TCLKA input when channels 1 and 5 are set to phase counting
mode.
TPU Channel
0 Setting (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001× B'0010 B'0011
IOC3 to IOC0 B'0000
B'0100
B'1×××
B'0001 to
B'0011
B'0101 to
B'0111
B'××00 Other than B'××00
CCLR2 to
CCLR0
— — — — Other
than
B'101
B'101
Output
function
— Output
compare
output
— PWM
mode 1
output*
3
PWM
mode 2
output
—
×: Don’t care
Note: 3. TIOCD0 output is disabled.
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting
(2) applies.