Datasheet

Rev.6.00 Oct.28.2004 page 261 of 1016
REJ09B0138-0600H
Read Write Read Write
Address
ø
DTC activation
request
DTC
request
Data transfer Data transfer
Transfer
information
write
Transfer
information
write
Transfer
information
read
Transfer
information
read
Vector read
Figure 8-12 DTC Operation Timing (Example of Chain Transfer)
8.3.10 Number of DTC Execution States
Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for
each execution status.
Table 8-8 DTC Execution Statuses
Mode
Vector Read
I
Register Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal 1 6 1 1 3
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
N: Block size (initial setting of CRAH and CRAL)
Table 8-9 Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM
On-
Chip
ROM
On-Chip I/O
Registers External Devices
Bus width 32 16 8 16 8 16
Access states 11222323
Execution Vector read S
I
— 1 — — 4 6+2m 2 3+m
status
Register
information
read/write
S
J
1 ———————
Byte data read S
K
112223+m23+m
Word data read S
K
114246+2m 2 3+m
Byte data write S
L
112223+m23+m
Word data write S
L
114246+2m 2 3+m
Internal operation S
M
1