Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 128 (14x20) 16-Bit 20 MHz I/O number 87

271

272

273

274

275

276

277

278

279

280

Rev.6.00 Oct.28.2004 page 246 of 1016

REJ09B0138-0600H

8.2.3 DTC Source Address Register (SAR)

Bit :2322212019 – – – 43210

– – –

Initial value :

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

– – – Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

R/W :————— – – – —————

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer,

specify an even source address.

8.2.4 DTC Destination Address Register (DAR)

Bit :2322212019 – – – 43210

– – –

Initial value :

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

– – – Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

R/W :————— – – – —————

DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size

transfer, specify an even destination address.

8.2.5 DTC Transfer Count Register A (CRA)

Bit :1514131211109876543210

Initial value :

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

R/W :————————————————

← CRAH → ← CRAL →

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time

data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits

(CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is

decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This

operation is repeated.

8.2.6 DTC Transfer Count Register B (CRB)

Bit :1514131211109876543210

Initial value :

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

R/W :————————————————