Datasheet

Rev.6.00 Oct.28.2004 page 237 of 1016
REJ09B0138-0600H
7.7 Usage Notes
DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting
state) channel setting should not be changed. The operating channel setting should only be changed when transfer is
disabled.
Also, the DMAC register should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
(a) DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is
updated in the bus cycle before DMAC transfer.
Figure 7-40 shows an example of the update timing for DMAC registers in dual address transfer mode.
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of a block
in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Notes: 1. In single address transfer mode, the update timing is the same as [1].
2. The MAR operation is post-incrementing/decrementing of the DMA internal address value.
[3]
[2'][2]
[1]
[1]
DMA transfer cycle
DMA read
DMA read
DMA write
DMA write
DMA
dead
DMA Internal
address
DMA control
DMA register
operation
DMA last transfer cycle
Transfer
destination
Transfer
destination
Transfer
source
Transfer
source
Idle
Idle
IdleRead
Read
Dead
Write
Write
ø
Figure 7-40 Example of DMAC Register Update Timing