Datasheet

Rev.6.00 Oct.28.2004 page 227 of 1016
REJ09B0138-0600H
Single Address Mode (Write): Figure 7-29 shows a transfer example in which TEND output is enabled and byte-size
single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
DMA write
ø
Address bus
DMA
dead
HWR
DACK
TEND
Bus
release
LWR
DMA write DMA write DMA write
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7-29 Example of Single Address Mode (Byte Write) Transfer
Figure 7-30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer
(write) is performed from an external device to external 8-bit, 2-state access space.
DMA write
ø
Address bus
DMA write DMA write
DMA
dead
HWR
TEND
DACK
Bus
release
LWR
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7-30 Example of Single Address Mode (Word Write) Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the
bus is released one or more bus cycles are inserted by the CPU or DTC.