Datasheet

Rev.6.00 Oct.28.2004 page 213 of 1016
REJ09B0138-0600H
Acquire bus
ETCRAL = ETCRAL–1
Transfer request?
ETCRAL = H'00
Release bus
BLKDIR = 0
ETCRAL = ETCRAH
ETCRB = ETCRB – 1
ETCRB = H'0000
Start
(DTE = DTME = 1)
Read address specified by MARA
MARA = MARA + SAIDE·(–1)
SAID
·2
DTSZ
Write to address specified by MARB
MARB = MARB + DAIDE·(–1)
DAID
·2
DTSZ
MARB = MARB – DAIDE·( – 1)
DAID
·2
DTSZ
·ETCRAH
MARA = MARA
– SAIDE·(–1)
SAID
·2
DTSZ
·ETCRAH
No
Yes
No
Yes
No
Yes
No
Yes
Clear DTE bit to 0
to end transfer
Figure 7-15 Operation Flow in Block Transfer Mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI
transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A
interrupts.
For details, see section 7.3.4, DMA Control Register (DMACR).
Figure 7-16 shows an example of the setting procedure for block transfer mode.