Datasheet

Rev.6.00 Oct.28.2004 page 177 of 1016
REJ09B0138-0600H
7.2.5 DMA Band Control Register (DMABCR)
Bit :1514131211109 8
DMABCRH : FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Bit:76543210
DMABCRL : DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
DMABCR is initialized to H'0000 by a reset, and in hardware standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address
mode.
Bit 15
FAE1 Description
0 Short address mode (Initial value)
1 Full address mode
In short address mode, channels 1A and 1B are used as independent channels.
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address
mode.
Bit 14
FAE0 Description
0 Short address mode (Initial value)
1 Full address mode
In short address mode, channels 0A and 0B are used as independent channels.
Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode
or single address mode.
Bit 13
SAE1 Description
0 Transfer in dual address mode (Initial value)
1 Transfer in single address mode
This bit is invalid in full address mode.