Datasheet

Rev.6.00 Oct.28.2004 page 161 of 1016
REJ09B0138-0600H
6.10.4 Transition Timing
Figure 6-37 shows the timing for transition to the bus-released state.
CPU
cycle
External bus released stateCPU cycle
Address
T
0
T
1
T
2
ø
Address bus
Data bus
AS
HWR, LWR
BREQ
BACK
High impedance
Minimum
1 state
BREQO
*
[1] [2] [3] [4] [5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Note: * Output only when BREQOE is set to 1.
Low level of BREQ pin is sampled at rise of T
2
state.
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
BREQO signal goes high 1.5 clocks after BACK signal goes high.
High impedance
High impedance
High impedance
RD
High impedance
Figure 6-37 Bus-Released State Transition Timing
6.10.5 Usage Note
When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts.
Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep
mode.