Datasheet

Rev.6.00 Oct.28.2004 page 157 of 1016
REJ09B0138-0600H
6.8.3 Pin States in Idle Cycle
Table 6-8 shows pin states in an idle cycle.
Table 6-8 Pin States in Idle Cycle
Pins Pin State
A
23
to A
0
Contents of next bus cycle
D
15
to D
0
High impedance
CSn*
2
High*
1
CAS High
AS High
RD High
HWR High
LWR High
DACKm*
3
High
Notes: 1. Remains low in DRAM space RAS down mode or a refresh cycle.
2. n = 0 to 7
3. m = 0, 1