Datasheet

Rev.6.00 Oct.28.2004 page 156 of 1016
REJ09B0138-0600H
T
1
Address bus
ø
RD
External read
Data bus
T
2
T
3
T
p
T
r
DRAM space read
T
c1
T
c2
Figure 6-34 Example of DRAM Access after External Read
T
p
T
r
T
c1
T
c2
T
I
T
1
T
2
T
3
T
cI
T
c2
T
c1
EXTAL
Address
RD
RAS
CAS, LCAS
Data bus
DRAM space read External read DRAM space read
Idle cycle
Figure 6-35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1)
T
p
T
r
T
c1
T
c2
T
I
T
1
T
2
T
3
T
cI
T
c2
T
c1
EXTAL
Address
RD
RAS
CAS, LCAS
Data bus
DRAM space read External read DRAM space write
Idle cycle
HWR
Figure 6-35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1)