Datasheet

Rev.6.00 Oct.28.2004 page 150 of 1016
REJ09B0138-0600H
6.6.2 When DDS = 0
When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The
DACK output goes low from the T
r
state in the case of the DRAM interface.
In modes other than DMAC single address mode, burst access can be used when accessing DRAM space.
Figure 6-29 shows the DACK output timing for the DRAM interface when DDS = 0.
T
p
ø
Read
Write
CSn, (RAS)
HWR, (WE)
D
15
to D
0
HWR, (WE)
DACK
D
15
to D
0
A
23
to A
0
T
r
T
c1
T
c2
Row Column
CAS, (UCAS),
LCAS, (LCAS)
Note: n = 2 to 5
Figure 6-29 DACK Output Timing when DDS = 0 (Example of DRAM Access)
6.7 Burst ROM Interface
6.7.1 Overview
With the H8S/2357 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can
be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be
accessed at high speed.
Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a
maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for
burst access.