Datasheet

Rev.6.00 Oct.28.2004 page 149 of 1016
REJ09B0138-0600H
T
Rp
ø
CSn, (RAS)
T
Rcr
CAS, LCAS
HWR, (WE)
T
Rc3
Software
standby
Note: n = 2 to 5
High
Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0)
6.6 DMAC Single Address Mode and DRAM Interface
When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When
DRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed
is selected.
6.6.1 When DDS = 1
Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low
from the T
C1
state in the case of the DRAM interface.
Figure 6-28 shows the DACK output timing for the DRAM interface when DDS = 1.
T
p
ø
Read
Write
CSn, (RAS)
HWR, (WE)
D
15
to D
0
HWR, (WE)
DACK
D
15
to D
0
A
23
to A
0
T
r
T
c1
T
c2
Row Column
CAS, (UCAS),
LCAS, (LCAS)
Note: n = 2 to 5
Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access)