Datasheet

Rev.6.00 Oct.28.2004 page 143 of 1016
REJ09B0138-0600H
6.5.9 Byte Access Control
When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for
byte access.
When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the control timing in the 2-
CAS system, and figure 6-19 shows an example 2-CAS system DRAM connection.
When only DRAM with a ×8 configuration is connected, set the CW2 bit to 1 in MCR.
T
p
ø
CSn, (RAS)
Byte control
A
23
to A
0
T
r
T
c1
T
c2
Row
CAS
LCAS
HWR, (WE)
Column
Note: n = 2 to 5
Figure 6-18 2-CAS System Control Timing (Upper Byte Write Access)
H8S/2357 Group
(Address shift size set to 9 bits)
CS, (RAS)
2-CAS type 4-Mbit DRAM
256-kbyte x 16-bit configuration
9-bit column address
OE
RAS
CAS UCAS
LCAS
LCAS
HWR, (WE)
WE
A
9
A
8
A
8
A
7
A
7
A
6
A
6
A
5
A
5
A
4
A
4
A
3
A
3
A
2
A
2
A
1
A
1
A
0
D
15
to D
0
D
15
to D
0
Low address
input: A
8
to A
0
Column address
input: A
8
to A
0
Figure 6-19 Example of 2-CAS System Connection