Datasheet

Rev.6.00 Oct.28.2004 page 141 of 1016
REJ09B0138-0600H
6.5.7 Precharge State Control
When DRAM is accessed, RAS precharging time must be secured. With the H8S/2357 Series, one T
p
state is always
inserted when DRAM space is accessed. This can be changed to two T
p
states by setting the TPC bit in MCR to 1. Set the
appropriate number of T
p
cycles according to the DRAM connected and the operating frequency of the H8S/2357 Group.
Figure 6-16 shows the timing when two T
p
states are inserted.
When the TPC bit is set to 1, two T
p
states are also used for refresh cycles.
T
p1
ø
CSn, (RAS)
Read
Write
CAS, LCAS
D
15
to D
0
D
15
to D
0
A
23
to A
0
T
p2
T
r
T
c1
Row Column
T
c2
HWR, (WE)
HWR, (WE)
Note: n = 2 to 5
Figure 6-16 Timing with Two Precharge States
6.5.8 Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using
the WAIT pin.
Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from
0 to 3 wait states can be inserted automatically between the T
c1
state and T
c2
state, according to the settings of WCRH and
WCRL.
Pin Wait Insertion: When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled
regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first
inserted. If the WAIT pin is low at the falling edge of ø in the last T
c1
or T
w
state, another T
w
state is inserted. If the WAIT
pin is held low, T
w
states are inserted until it goes high.