Rev.6.00 Oct.28.2004 page 134 of 1016
REJ09B0138-0600H
Bus cycle
T
1
T
2
Address bus
ΓΈ
CSn
AS
RD
D
15
to
D
8
Invalid
D
7
to
D
0
Valid
Read
HWR
LWR
D
15
to
D
8
High impedance
D
7
to
D
0
Valid
Write
High
Note: n = 0 to 7
T
3
Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
