Datasheet

Rev.6.00 Oct.28.2004 page 122 of 1016
REJ09B0138-0600H
6.3.2 Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access states, and number of
program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by
the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected
functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus
mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is
selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access
space.
With the DRAM interface and burst ROM interface, the number of access states may be determined without regard to
ASTCR.
When 2-state access space is designated, wait insertion is disabled.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait
states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected.
Table 6-3 shows the bus specifications for each basic bus interface area.
Table 6-3 Bus Specifications for Each Area (Basic Bus Interface)
WCRH, WCRL Bus Specifications (Basic Bus Interface)
ABWCR
ABWn
ASTCR
ASTn Wn1 Wn0 Bus Width Access States
Program Wait
States
00——16 2 0
100 3 0
11
10 2
13
10——8 2 0
100 3 0
11
10 2
13