Datasheet

Rev.6.00 Oct.28.2004 page 105 of 1016
REJ09B0138-0600H
6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the bus controller.
Area decoder
Bus controller
ABWCR
ASTCR
BCRH
BCRL
Internal
address bus
CS0 to CS7
External bus control signals
BREQ
BACK
BREQO
Internal control
signals
Wait controller
WCRH
WCRL
Bus mode signal
DRAM controller
RTCNT
RTCOR
DRAMCR
MCR
Bus arbiter
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
External DRAM
signals
WAIT
Internal data bus
Figure 6-1 Block Diagram of Bus Controller