Datasheet

Rev.6.00 Oct.28.2004 page 91 of 1016
REJ09B0138-0600H
Origin of
Vector
Address*
Interrupt Source
Interrupt
Source
Vector
Number
Advanced
Mode IPR Priority
ERI0 (receive error 0)
RXI0 (reception data full 0)
TXI0 (transmit data empty 0)
TEI0 (transmission end 0)
SCI
channel 0
80
81
82
83
H'0140
H'0144
H'0148
H'014C
IPRJ2 to 0 High
ERI1 (receive error 1)
RXI1 (reception data full 1)
TXI1 (transmit data empty 1)
TEI1 (transmission end 1)
SCI
channel 1
84
85
86
87
H'0150
H'0154
H'0158
H'015C
IPRK6 to 4
ERI2 (receive error 2)
RXI2 (reception data full 2)
TXI2 (transmit data empty 2)
TEI2 (transmission end 2)
SCI
channel 2
88
89
90
91
H'0160
H'0164
H'0168
H'016C
IPRK2 to 0
Low
Note: * Lower 16 bits of the start address.
5.4 Interrupt Operation
5.4.1 Interrupt Control Modes and Interrupt Operation
Interrupt operations in the H8S/2357 Group differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ
interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to
0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the
interrupt controller.
Table 5-5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0
bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2
to I0 in EXR.
Table 5-5 Interrupt Control Modes
Interrupt
SYSCR
Priority Setting Interrupt
Control Mode INTM1 INTM0 Registers Mask Bits Description
0 0 0 — I Interrupt mask control is
performed by the I bit.
— 1 — — Setting prohibited
2 1 0 IPR I2 to I0 8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set with
IPR.
— 1 — — Setting prohibited