Datasheet

Rev.6.00 Oct.28.2004 page 89 of 1016
REJ09B0138-0600H
Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Vector
Address*
Interrupt Source
Interrupt
Source
Vector
Number
Advanced
Mode IPR Priority
NMI External 7 H'001C — High
IRQ0
pin
16 H'0040 IPRA6 to 4
IRQ1 17 H'0044 IPRA2 to 0
IRQ2
IRQ3
18
19
H'0048
H'004C
IPRB6 to 4
IRQ4
IRQ5
20
21
H'0050
H'0054
IPRB2 to 0
IRQ6
IRQ7
22
23
H'0058
H'005C
IPRC6 to 4
SWDTEND (software activation
interrupt end)
DTC 24 H'0060 IPRC2 to 0
WOVI (interval timer) Watchdog
timer
25 H'0064 IPRD6 to 4
CMI (compare match) Refresh
controller
26 H'0068 IPRD2 to 0
Reserved — 27 H'006C IPRE6 to 4
ADI (A/D conversion end) A/D 28 H'0070 IPRE2 to 0
Reserved — 29
30
31
H'0074
H'0078
H'007C
TGI0A (TGR0A input capture/
compare match)
TGI0B (TGR0B input capture/
compare match)
TGI0C (TGR0C input capture/
compare match)
TGI0D (TGR0D input capture/
compare match)
TCI0V (overflow 0)
TPU
channel 0
32
33
34
35
36
H'0080
H'0084
H'0088
H'008C
H'0090
IPRF6 to 4
Reserved — 37
38
39
H'0094
H'0098
H'009C
TGI1A (TGR1A input capture/
compare match)
TGI1B (TGR1B input capture/
compare match)
TCI1V (overflow 1)
TCI1U (underflow 1)
TPU
channel 1
40
41
42
43
H'00A0
H'00A4
H'00A8
H'00AC
IPRF2 to 0
TGI2A (TGR2A input capture/
compare match)
TGI2B (TGR2B input capture/
compare match)
TCI2V (overflow 2)
TCI2U (underflow 2)
TPU
channel 2
44
45
46
47
H'00B0
H'00B4
H'00B8
H'00BC
IPRG6 to 4
Low