Datasheet

Rev.6.00 Oct.28.2004 page 86 of 1016
REJ09B0138-0600H
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCRH
Bit :1514131211109 8
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
ISCRL
Bit:76543210
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level
sensing, for the input at pins IRQ7 to IRQ0.
ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.
Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA,
IRQ0SCB)
Bits 15 to 0
IRQ7SCB to
IRQ0SCB
IRQ7SCA to
IRQ0SCA Description
0 0 Interrupt request generated at IRQ7 to IRQ0 input low level
(Initial value)
1 Interrupt request generated at falling edge of IRQ7 to IRQ0 input
1 0 Interrupt request generated at rising edge of IRQ7 to IRQ0 input
1 Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input
5.2.5 IRQ Status Register (ISR)
Bit:76543210
IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
Initial value : 0 0 0 0 0 0 0 0
R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests.