Datasheet

Rev.6.00 Oct.28.2004 page 84 of 1016
REJ09B0138-0600H
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes
for the interrupt controller.
Bit 5
INTM1
Bit 4
INTM0
Interrupt
Control Mode Description
0 0 0 Interrupts are controlled by I bit (Initial value)
1 — Setting prohibited
1 0 2 Interrupts are controlled by bits I2 to I0, and IPR
1 — Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG Description
0 Interrupt request generated at falling edge of NMI input (Initial value)
1 Interrupt request generated at rising edge of NMI input
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)
Bit:76543210
— IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
Initial value : 0 1 1 1 0 1 1 1
R/W : — R/W R/W R/W — R/W R/W R/W
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than
NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits cannot be modified and are always read as 0.