Datasheet

Rev.6.00 Oct.28.2004 page 82 of 1016
REJ09B0138-0600H
5.1.2 Block Diagram
A block diagram of the interrupt controller is shown in Figure 5-1.
SYSCR
NMI input
IRQ input
Internal interrupt
request
SWDTEND to TEI
INTM1, INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
IPR
Interrupt controller
Priority
determination
Interrupt
request
Vector
number
I
I2 to I0
CCR
EXR
CPU
ISCR:
IER:
ISR:
IPR:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register
System control register
Legend:
Figure 5-1 Block Diagram of Interrupt Controller
5.1.3 Pin Configuration
Table 5-1 summarizes the pins of the interrupt controller.
Table 5-1 Interrupt Controller Pins
Name Symbol I/O Function
Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or
falling edge can be selected
External interrupt
requests 7 to 0
IRQ7 to IRQ0 Input Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected