Datasheet

Rev.6.00 Oct.28.2004 page 1009 of 1016
REJ09B0138-0600H
Port Name
Pin Name
MCU
Operating
Mode
Power-
On
Reset
Manual
Reset*
2
Hardware
Standby
Mode
Software
Standby
Mode
Bus
Release
State
Program
Execution
State
Sleep Mode
PF
2
/LCAS/
WAIT/
BREQO
4 to 6 T [BREQOE +
WAITE +
LCASE = 0]
kept
[BREQOE = 1]
BREQO
[WAITE = 1]
T
[LCASE = 1]
H*
1
T [BREQOE +
WAITE +
LCASE = 0]
kept
[BREQOE = 1]
kept
[WAITE = 1]
T
[LCASE = 1,
OPE = 0]
T
[LCASE = 1,
OPE = 1]
LCAS
[BREQOE +
WAITE +
LCASE = 0]
kept
[BREQOE = 1]
BREQO
[WAITE = 1]
T
[LCASE = 1]
T
[BREQOE +
WAITE +
LCASE= 0]
I/O port
[BREQOE = 1]
BREQO
[WAITE = 1]
WAIT
[LCASE = 1]
LCAS
7 T kept T kept kept I/O port
PF
1
/BACK 4 to 6 T [BRLE = 0]
kept
[BRLE = 1]
BACK
T [BRLE = 0]
kept
[BRLE = 1]
H
L [BRLE = 0]
I/O port
[BRLE = 1]
BACK
7 T kept T kept kept I/O port
PF
0
/BREQ 4 to 6 T [BRLE = 0]
kept
[BRLE = 1]
BREQ
T [BRLE = 0]
kept
[BRLE = 1]
T
T [BRLE = 0]
I/O port
[BRLE = 1]
BREQ
PG
4
/CS0 4, 5 H [DDR = 0] T [DDR · OPE = 0] T [DDR = 0]
6T
T
[DDR = 1]
H*
1
T
[DDR · OPE = 1]
H
Input port
[DDR = 1]
CS0
7 T kept T kept kept I/O port
PG
3
/CS1
PG
2
/CS2
PG
1
/CS3
7
4 to 6
T
T
kept
[DDR = 0]
T
[DDR = 1]
H*
1
T
T
kept
[DDR · OPE = 0]
T
[DDR · OPE = 1]
H
kept
T
I/O port
[DDR = 0]
Input port
[DDR = 1]
CS1 to CS3
PG
0
/CAS 7 T kept T kept kept I/O port
4 to 6 T [DRAME = 0]
kept
[DRAME = 1]
H*
1
T [DRAME = 0]
kept
[OPE = 0]
T
[DRAME ·
OPE= 1]
CAS
T [DRAME = 0]
Input port
[DRAME = 1]
CAS
Legend:
H: High level
L: Low level
T: High impedance
kept: Input port becomes high-impedance, output port retains state
DDR: Data direction register
OPE: Output port enable
WAITE: Wait input enable
BRLE: Bus release enable