Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 128 (14x20) 16-Bit 20 MHz I/O number 87

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (1049 pages)

PAGE 1
To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
PAGE 2
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
PAGE 3
User’s Manual 16 H8S/2357 Group, H8S/2357F-ZTATTM, H8S/2398F-ZTATTM Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp.
PAGE 4
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
PAGE 5
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
PAGE 6
PAGE 7
Preface This LSI is a single-chip microcomputer with a 32-bit H8S/2000 CPU core, and a set of on-chip peripheral functions required for system configuration. This LSI is equipped with ROM, RAM, a bus controller, a data transfer controller (DTC), a programmable pulse generator (PPG), three types of timers, a serial communication interface (SCI), a D/A converter, an A/D converter, and I/O ports as on-chip peripheral functions.
PAGE 8
User's manuals for development tools: Manual Title Document No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual REJ10B0058 H8S, H8/300 Series Simulator/Debugger (for Windows) User's Manual ADE-702-037 H8S, H8/300 Series High-performance Embedded Workshop User's Manual ADE-702-201 Application Note: Manual Title Document No. H8S Family Technical Q & A REJ05B0397 Rev.6.00 Oct.28.
PAGE 9
Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.1 Overview 5 Product lineup HD64F2398F20T*3 and HD64F2398TE20T*3 added Table 1-1 Overview 5V version F-ZTAT Version* HD64F2357F20 HD64F2398F20 HD64F2357TE20 HD64F2398TE20 HD64F2398F20T * 3 HD64F2398TE20T* 3 Note 3 added as follows Note: 3. For the HD64F2398F20T and HD64F2398TE20T only, the maximum number of times the flash memory can be reprogrammed is 1,000. 4.1.
PAGE 10
Item Page Revision (See Manual for Details) 9.8.2 Register Configuration 303 Note added Port A MOS Pull-Up Control Register (PAPCR) (ON-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : R/W Note: 304 : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PAGE 11
Item Page Revision (See Manual for Details) 9.12.2 Register Configuration 324 Note added Port E MOS Pull-Up Control Register (PEPCR) (ON-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W Note: 10.4.5 Cascaded Operation 383 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PAGE 12
Item Page Revision (See Manual for Details) 19.18.2 Program-Verify Mode 639 Figure 19-48 amended, note *6 added Figure 19-48 Program/ProgramVerify Flowchart Write pulse application subroutine Start of programming Sub-routine write pulse Start Enable WDT Set SWE bit in FLMCR1 Wait (x) µs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU bit in FLMCR1 Wait (y) µs *6 Perform programming in the erased state.
PAGE 13
Instruction 1 Advanced R:W NEXT Advanced R:W 2nd JSR @@aa:8 Advanced R:W NEXT JSR @ERn JSR @aa:24 3 R:W aa:8 4 5 Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) 2 R:W:M aa:8 R:W EA 6 7 8 9 Table A-6 Instruction Execution Cycles JMP @@aa:8 Advanced R:W NEXT Item Page Revision (See Manual for Details) A.
PAGE 14
Item Page Revision (See Manual for Details) G. Product Code Lineup 1014 Table G-2 amended Table G-2 H8S/2398, H8S/2394, H8S/2392, H8S/2390 Group Product Code Lineup Product Type H8S/2398 Masked ROM F-ZTAT H. Package Dimensions Figure H-1 TFP-120 Package Dimension Rev.6.00 Oct.28.
PAGE 15
Contents Section 1 Overview...............................................................................................................................1 1.1 1.2 1.3 Overview....................................................................................................................................................................... 1 Block Diagram........................................................................................................................................................
PAGE 16
Section 3 MCU Operating Modes ......................................................................................................55 3.1 3.2 3.3 3.4 3.5 Overview..................................................................................................................................................................... 55 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) ................................................................................. 55 3.1.
PAGE 17
5.3 5.4 5.5 5.6 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ..................................................................................... 84 5.2.3 IRQ Enable Register (IER) ........................................................................................................................... 85 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..............................................................................86 5.2.5 IRQ Status Register (ISR) ..................
PAGE 18
6.4.5 Wait Control ................................................................................................................................................136 6.5 DRAM Interface....................................................................................................................................................... 138 6.5.1 Overview ..................................................................................................................................................... 138 6.
PAGE 19
7.4 7.5 7.6 7.7 7.3.1 Memory Address Register (MAR) ..............................................................................................................181 7.3.2 I/O Address Register (IOAR)......................................................................................................................181 7.3.3 Execute Transfer Count Register (ETCR)................................................................................................... 181 7.3.4 DMA Control Register (DMACR)......
PAGE 20
8.4 8.5 8.3.7 Block Transfer Mode................................................................................................................................... 258 8.3.8 Chain Transfer............................................................................................................................................. 259 8.3.9 Operation Timing ........................................................................................................................................260 8.3.
PAGE 21
9.11.2 Register Configuration (On-Chip ROM Version Only)..............................................................................318 9.11.3 Pin Functions............................................................................................................................................... 320 9.11.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)....................................................................321 9.12 Port E ..............................................................
PAGE 22
10.7 Usage Notes ..............................................................................................................................................................404 Section 11 Programmable Pulse Generator (PPG) ...........................................................................411 11.1 Overview................................................................................................................................................................... 411 11.1.1 Features ..........
PAGE 23
12.6.2 12.6.3 12.6.4 12.6.5 12.6.6 Contention between TCNT Write and Increment ....................................................................................... 449 Contention between TCOR Write and Compare Match ............................................................................. 450 Contention between Compare Matches A and B ........................................................................................450 Switching of Internal Clocks and TCNT Operation............................
PAGE 24
14.4 SCI Interrupts ........................................................................................................................................................... 512 14.5 Usage Notes ..............................................................................................................................................................514 Section 15 Smart Card Interface.......................................................................................................517 15.1 Overview.
PAGE 25
17.2.2 D/A Control Register (DACR)....................................................................................................................557 17.2.3 Module Stop Control Register (MSTPCR) ................................................................................................. 558 17.3 Operation ..................................................................................................................................................................559 Section 18 RAM...............
PAGE 26
19.11 19.12 19.13 19.14 19.15 19.16 19.17 19.18 19.19 19.20 19.21 19.22 19.10.3 Error Protection ........................................................................................................................................... 599 Flash Memory Emulation in RAM........................................................................................................................... 601 19.11.1 Emulation in RAM ................................................................................
PAGE 27
19.22.2 Socket Adapters and Memory Map............................................................................................................. 648 19.22.3 Programmer Mode Operation......................................................................................................................650 19.22.4 Memory Read Mode....................................................................................................................................651 19.22.5 Auto-Program Mode ...................
PAGE 28
22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.1.3 AC Characteristics....................................................................................................................................... 684 22.1.4 A/D Conversion Characteristics ..................................................................................................................701 22.1.5 D/A Conversion Characteristics ..................................................................................................................
PAGE 29
C.12 Port F Block Diagram............................................................................................................................................... 996 C.13 Port G Block Diagram ............................................................................................................................................1004 Appendix D Pin States ....................................................................................................................1007 D.
PAGE 30
Rev.6.00 Oct.28.
PAGE 31
Section 1 Overview 1.1 Overview The H8S/2357 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
PAGE 32
Table 1-1 Overview Item Specification CPU • • • • • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control  Maximum clock rate: 20 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 50 ns 16 × 16-bit register-register multiply: 1000 ns 32 ÷ 16-bit register-register divide: 1000 ns Instruction set suitable for high-speed operation  Sixty-five bas
PAGE 33
Item Specification 16-bit timer-pulse unit (TPU) • • • 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins Automatic 2-phase encoder count capability Programmable pulse generator (PPG) • • • • Maximum 16-bit pulse output possible with TPU as time base Output trigger selectable in 4-bit groups Non-overlap margin can be set Direct output or inverse output setting possible 8-bit timer 2 channels • • • 8-bit up-counter (external event count capability) Two time constant re
PAGE 34
Item Specification Interrupt controller • • • Nine external interrupt pins (NMI, IRQ0 to IRQ7) 52 internal interrupt sources Eight priority levels settable Power-down state • • • • • Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Operating modes • Eight MCU operating modes (H8S/2357 F-ZTAT) External Data Bus CPU Operating Mode Mode Description On-Chip Initial ROM Value Maximum Value 0 — — — — — 1 2 3 4 5 Advanced On-chip ROM disabled expansion
PAGE 35
Item Operating modes Specification • Four MCU operating modes (H8S/2398 F-ZTAT, masked ROM, ROMless, and ZTAT) Mode 0 1 2* 1 3* 1 4* 2 CPU Operating Mode — Description — On-Chip ROM — External Data Bus Initial Maximum Value Value — — Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode 5* 2 On-chip ROM disabled Disabled 8 bits 16 bits expansion mode 6 On-chip ROM enabled Enabled 8 bits 16 bits expansion mode 7 Single-chip mode Enabled — — Notes: 1.
PAGE 36
1.
PAGE 37
1.3 Pin Description 1.3.
PAGE 38
P53 /ADTRG P52 /SCK2 VSS VSS P51 /RxD2 P50 /TxD2 PF0 /BREQ PF1 /BACK PF2 /LCAS/WAIT/BREQO PF3 /LWR PF4 /HWR PF5 /RD PF6 /AS VCC PF7 /ø VSS EXTAL XTAL VCC STBY NMI RES WDTOVF (FWE*) P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 /TEND1 P62 /DREQ1 P61 /TEND0/CS5 VSS VSS P60 /DREQ0/CS4 VSS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69
PAGE 39
P51 /RxD2 P50 /TxD2 PF0 /BREQ PF1 /BACK PF2 /LCAS/WAIT/BREQO PF3 /LWR PF4 /HWR PF5 /RD PF6 /AS VCC PF7 /ø VSS EXTAL XTAL VCC STBY NMI RES VCL P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 /TEND1 P62 /DREQ1 P61 /TEND0/CS5 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
PAGE 40
P53 /ADTRG P52 /SCK2 VSS VSS P51 /RxD2 P50 /TxD2 PF0 /BREQ PF1 /BACK PF2 /LCAS/WAIT/BREQO PF3 /LWR PF4 /HWR PF5 /RD PF6 /AS VCC PF7 /ø VSS EXTAL XTAL VCC STBY NMI RES VCL P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 /TEND1 P62 /DREQ1 P61 /TEND0/CS5 VSS VSS P60 /DREQ0/CS4 VSS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 6
PAGE 41
1.3.2 Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2357 Group in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No.
PAGE 42
Pin No.
PAGE 43
Pin No.
PAGE 44
Pin No.
PAGE 45
1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2357 Group. Table 1-3 Pin Functions Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Power VCC 81, 76, 52, 33, 1 89, 84, 58, 39, 5, Power supply: For connection to the power supply. All V CC pins should be connected to the system power supply.
PAGE 46
Pin No. Type Symbol Operating mode MD2 to control MD0 TFP-120 FP-128B I/O Name and Function 115 to 113 125 to 123 Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2357 Group is operating.
PAGE 47
Pin No. Type Symbol TFP-120 FP-128B I/O Address bus A23 to A0 28 to 25, 23 to 16, 14 to 7, 5 to 2 32 to 29, 27 to 20, 18 to 11, 9 to 6 Output Address bus: These pins output an address. Data bus D15 to D0 51 to 48, 46 to 39, 37 to 34 57 to 54, 52 to 45, 43 to 40 I/O Bus control CS7 to CS0 120 to 117 128, 127, Output Chip select: Signals for selecting areas 7 to 0.
PAGE 48
Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function 16-bit timerpulse unit (TPU) TCLKD to TCLKA 110, 109, 120, 119, Input 107, 105 117, 115 Clock input D to A: These pins input an external clock. TIOCA0, TIOCB0, TIOCC0, TIOCD0 112 to 109 122 to 119 I/O Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins.
PAGE 49
Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function A/D converter AN7 to AN0 102 to 95 112 to 105 Input Analog 7 to 0: Analog input pins. ADTRG 92 102 Input A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. D/A converter DA1, DA0 102, 101 112, 111 Output Analog output: D/A converter analog output pins. A/D converter and D/A converter AVCC 93 103 Input This is the power supply pin for the A/D converter and D/A converter.
PAGE 50
Pin No. Notes: 1. 2. 3. 4. Type Symbol TFP-120 FP-128B I/O Name and Function I/O ports PB7 to PB0 19 to 16, 14 to 11 23 to 20, 18 to 15 I/O Port B* 4: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). PC 7 to PC 0 10 to 7, 5 to 2 14 to 11, 9 to 6 I/O Port C* 4: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR).
PAGE 51
Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features.
PAGE 52
• Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU.
PAGE 53
2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. • Additional control register  One 8-bit control register has been added. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Two-bit shift instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added.
PAGE 54
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-1). For details of the exception vector table, see section 4, Exception Handling.
PAGE 55
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-2. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
PAGE 56
2.3 Address Space Figure 2-3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'00000000 Program area H'00FFFFFF Data area Cannot be used by the H8S/2357 Group H'FFFFFFFF Advanced Mode Figure 2-3 Memory Map Rev.6.00 Oct.28.
PAGE 57
2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2-4. There are two types of registers: general registers and control registers.
PAGE 58
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-5 illustrates the usage of the general registers. The usage of each register can be selected independently.
PAGE 59
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC.
PAGE 60
2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimaladjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2-7 shows the data formats in general registers.
PAGE 61
Data Type Register Number Word data Rn Data Format 15 0 MSB Word data En 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 LSB Rn Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats (cont) Rev.6.00 Oct.28.
PAGE 62
2.5.2 Memory Data Formats Figure 2-8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
PAGE 63
2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1.
PAGE 64
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use.
PAGE 65
2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below.
PAGE 66
Table 2-3 Instructions Classified by Function Type Instruction Size* 1 Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2357 Group. MOVTPE B Cannot be used in the H8S/2357 Group. POP W/L @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PAGE 67
Type Instruction Size* 1 Function Arithmetic operations DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder.
PAGE 68
Type Instruction Size* 1 Function Bitmanipulation instructions BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (
PAGE 69
Type Instruction Size* 1 Function Bitmanipulation instructions BST B C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B ¬ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
PAGE 70
Type Size* 1 Function B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP — PC + 2 → PC Only increments the program counter. EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.
PAGE 71
2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2-9 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc.
PAGE 72
Table 2-4 Addressing Modes No.
PAGE 73
Table 2-5 Absolute Address Access Ranges Absolute Address Advanced Mode Data address Program instruction address 8 bits (@aa:8) H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF 24 bits (@aa:24) (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly.
PAGE 74
Rev.6.00 Oct.28.
PAGE 75
Rev.6.00 Oct.28.2004 page 45 of 1016 REJ09B0138-0600H 6 op op abs op Immediate #xx:8/#xx:16/#xx:32 @aa:32 op @aa:24 @aa:16 op abs abs IMM abs Absolute address 5 @aa:8 Addressing Mode and Instruction Format No. Effective Address Calculation 24 23 24 23 24 23 Operand is immediate data.
PAGE 76
Rev.6.00 Oct.28.2004 page 46 of 1016 REJ09B0138-0600H 8 7 No.
PAGE 77
2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-11 shows a diagram of the processing states. Figure 2-12 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
PAGE 78
End of bus request Bus request Program execution state End of bus request Bus request SLEEP instruction with SSBY = 1 Bus-released state End of exception handling SLEEP instruction with SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1.
PAGE 79
Table 2-7 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows.
PAGE 80
Figure 2-13 shows the stack after exception handling ends. Advanced mode SP SP EXR Reserved* CCR CCR PC (24 bits) PC (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Note: *Ignored when returning. Figure 2-13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.
PAGE 81
(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 2.9 Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state.
PAGE 82
Bus cycle T1 ø Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2-15 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-16 shows the access timing for the on-chip supporting modules. Figure 2-17 shows the pin states.
PAGE 83
Bus cycle T1 T2 ø Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2-17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 2.10 Usage Note 2.10.
PAGE 84
Rev.6.00 Oct.28.
PAGE 85
Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) The H8S/2357 F-ZTAT has eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings. The CPU operating mode and initial bus width can be selected as shown in table 3-1. Table 3-1 lists the MCU operating modes.
PAGE 86
The H8S/2357 F-ZTAT can only be used in modes 4 to 7, 10, 11, 14, and 15. This means that the flash write enable pin and mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Operating Mode Selection (ZTAT, Masked ROM, ROMless Version, and H8S/2398 F-ZTAT) The H8S/2357 Group has four operating modes (modes 4 to 7).
PAGE 87
3.1.3 Register Configuration The H8S/2357 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and a system control register 2 (SYSCR2)*2 that control the operation of the H8S/2357 Group. Table 3-3 summarizes these registers.
PAGE 88
Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit cannot be modified and is always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation.
PAGE 89
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19, ROM. Bit 3 FLSHE Description 0 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) 1 Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Oct.28.
PAGE 90
3.3 Operating Mode Descriptions 3.3.1 Mode 1 Mode 1 is not supported in this LSI, and must not be set. 3.3.2 Mode 2 (H8S/2398 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU operation is the same as in mode 6. 3.3.3 Mode 3 (H8S/2398 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU operation is the same as in mode 7. 3.3.
PAGE 91
3.3.7 Mode 7 (Single-Chip Mode) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 3.3.8 Modes 8 and 9 Modes 8 and 9 are not supported in the H8S/2357 Group, and must not be set. 3.3.9 Mode 10 (H8S/2357 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU operation is the same as in mode 6. 3.3.
PAGE 92
3.4 Pin Functions in Each Operating Mode The pin functions of ports A to F vary depending on the operating mode. Table 3-4 shows their functions in each operating mode.
PAGE 93
Modes 4 and 5*4 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space On-chip ROM H'00FFFF H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'01FFFF H'020000 H'FFDC00 External address space H'FFDC00 On-chip RAM*3 H'FFDC00 On-chip RAM*3 On-chip RAM H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal
PAGE 94
Mode 10*4 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11*4 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'01FFFF H'020000 External address space H'FFDC00 H'FFDC00 *3 On-chip RAM*3 On-chip RAM H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF H'FFFE40 H'FFFF07
PAGE 95
Mode 14*4 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15*4 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'01FFFF H'020000 External address space H'FFDC00 H'FFDC00 *3 On-chip RAM*3 On-chip RAM H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF H'
PAGE 96
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 H'FFEC00 Reserved space*1 On-chip RAM*2 H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. This is a reserved space. Access to this space is inhibited. The space can be made available for use as an external address space by clearing the RAME bit of the SYSCR to 0. 2.
PAGE 97
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM* H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-3 Memory Map in Each Operating Mode (H8S/2392) Rev.6.00 Oct.28.
PAGE 98
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FF7C00 On-chip RAM* H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-4 Memory Map in Each Operating Mode (H8S/2394) Rev.6.00 Oct.28.
PAGE 99
Mode 2*5 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 3*5 (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2*4 H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00 On-chip On-chip RAM*3 RAM*3 H'FFFBFF H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF External address space Internal I/O registers External address space Internal I/O registers H'FFFE40 H'FFFF07 Internal I/O regist
PAGE 100
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space On-chip ROM H'00FFFF H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2*4 H'03FFFF H'040000 H'FFDC00 External address space H'FFDC00 On-chip RAM*3 H'FFDC00 On-chip RAM*3 On-chip RAM H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal
PAGE 101
Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state.
PAGE 102
4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.
PAGE 103
Table 4-2 Exception Vector Table Vector Address* 1 Exception Source Vector Number Advanced Mode Power-on reset 0 H'0000 to H'0003 3 1 H'0004 to H'0007 2 H'0008 to H'000B 3 H'000C to H'000F 4 H'0010 to H'0013 Trace 5 H'0014 to H'0017 Reserved for system use 6 H'0018 to H'001B External interrupt 7 H'001C to H'001F 8 H'0020 to H'0023 9 H'0024 to H'0027 10 H'0028 to H'002B 11 H'002C to H'002F 12 H'0030 to H'0033 13 H'0034 to H'0037 14 H'0038 to H'003B 15 H'003C to H'003F
PAGE 104
4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2357 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high.
PAGE 105
4.2.3 Reset Sequence The H8S/2357 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2357 Group is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2357 Group during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the H8S/2357 Group starts reset exception handling as follows: 1.
PAGE 106
4.2.4 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 4.2.
PAGE 107
4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4-3 classifies the interrupt sources and the number of interrupts of each type.
PAGE 108
4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4-5 shows the status of CCR and EXR after execution of trap instruction exception handling.
PAGE 109
4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2357 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.
PAGE 110
Rev.6.00 Oct.28.
PAGE 111
Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2357 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR  An interrupt priority register (IPR) is provided for setting interrupt priorities.
PAGE 112
5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1.
PAGE 113
5.1.4 Register Configuration Table 5-2 summarizes the registers of the interrupt controller.
PAGE 114
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 Bit 4 INTM0 Interrupt Control Mode Description 0 0 0 Interrupts are controlled by I bit 1 — Setting prohibited 0 2 Interrupts are controlled by bits I2 to I0, and IPR 1 — Setting prohibited 1 (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. 5.2.
PAGE 115
Table 5-3 Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 2 to 0 IPRA IRQ0 IRQ1 IPRB IRQ2 IRQ3 IRQ4 IRQ5 IPRC IRQ6 IRQ7 DTC IPRD Watchdog timer Refresh timer IPRE —* A/D converter IPRF TPU channel 0 TPU channel 1 IPRG TPU channel 2 TPU channel 3 IPRH TPU channel 4 TPU channel 5 IPRI 8-bit timer channel 0 8-bit timer channel 1 IPRJ DMAC SCI channel 0 IPRK SCI channel 1 SCI channel 2 Note: * Reserved bits.
PAGE 116
5.2.
PAGE 117
Bit n IRQnF Description 0 [Clearing conditions] 1 (Initial value) • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag • When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high • When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) • When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleare
PAGE 118
IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn interrupt S Q request R IRQn input Clear signal Note: n=7 to 0 Figure 5-2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output.
PAGE 119
Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 Origin of Interrupt Source External pin Vector Address* Vector Number Advanced Mode IPR Priority 7 H'001C — High 16 H'0040 IPRA6 to 4 IRQ1 17 H'0044 IPRA2 to 0 IRQ2 IRQ3 18 19 H'0048 H'004C IPRB6 to 4 IRQ4 IRQ5 20 21 H'0050 H'0054 IPRB2 to 0 IRQ6 IRQ7 22 23 H'0058 H'005C IPRC6 to 4 SWDTEND (software activation interrupt end) DTC 24 H'0060 IPRC2 to 0 WOVI (interval timer) Wat
PAGE 120
Interrupt Source Origin of Interrupt Source TGI3A (TGR3A input capture/ compare match) TPU channel 3 Vector Address* Vector Number Advanced Mode IPR Priority 48 H'00C0 IPRG2 to 0 High TGI3B (TGR3B input capture/ compare match) 49 H'00C4 TGI3C (TGR3C input capture/ compare match) 50 H'00C8 TGI3D (TGR3D input capture/ compare match) 51 H'00CC TCI3V (overflow 3) 52 H'00D0 Reserved — 53 54 55 H'00D4 H'00D8 H'00DC TGI4A (TGR4A input capture/ compare match) TPU channel 4 56 H'00E0
PAGE 121
Origin of Interrupt Source Vector Address* Vector Number Advanced Mode IPR Priority 80 H'0140 IPRJ2 to 0 High 81 H'0144 TXI0 (transmit data empty 0) 82 H'0148 TEI0 (transmission end 0) 83 H'014C 84 H'0150 85 H'0154 86 H'0158 87 H'015C 88 H'0160 Interrupt Source ERI0 (receive error 0) RXI0 (reception data full 0) ERI1 (receive error 1) RXI1 (reception data full 1) SCI channel 0 SCI channel 1 TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) RXI2 (rec
PAGE 122
Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Default priority determination Interrupt source Vector number 8-level mask control IPR I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5-6 shows the interrupts selected in each interrupt control mode.
PAGE 123
(3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending.
PAGE 124
Program execution status No Interrupt generated? Yes Yes NMI No No I=0 Hold pending Yes No IRQ0 Yes IRQ1 No Yes TEI2 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.6.00 Oct.28.
PAGE 125
5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
PAGE 126
Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Mask level 5 or below? Level 1 interrupt? No No Yes Yes Mask level 0 No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.6.00 Oct.28.
PAGE 127
(1) (2) (4) (3) Instruction prefetch Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
PAGE 128
5.4.5 Interrupt Response Times The H8S/2357 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5-9 are explained in table 510.
PAGE 129
5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction.
PAGE 130
5.5.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.
PAGE 131
5.6.2 Block Diagram Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller.
PAGE 132
If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC, the DTCE bit of DTCERA to DTCERF in the DTC and the DISEL bit of MRB in the DTC.
PAGE 133
Section 6 Bus Controller 6.1 Overview The H8S/2357 Group has a on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC). 6.1.
PAGE 134
• Other features  Refresh counter (refresh timer) can be used as an interval timer  External bus release function Rev.6.00 Oct.28.
PAGE 135
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller.
PAGE 136
6.1.3 Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read. High write/write enable HWR Output Strobe signal indicating that external space is to be written, and upper half (D 15 to D8) of data bus is enabled. 2-CAS DRAM write enable signal.
PAGE 137
6.1.4 Register Configuration Table 6-2 summarizes the registers of the bus controller.
PAGE 138
6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Modes 5 to 7 Initial value : R/W : Mode 4 Initial value : R/W : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.
PAGE 139
6.2.2 Access State Control Register (ASTCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space.
PAGE 140
6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT.
PAGE 141
Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
PAGE 142
Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1.
PAGE 143
6.2.4 Bus Control Register H (BCRH) Bit : Initial value : R/W : 7 6 5 4 ICIS1 ICIS0 1 1 0 1 R/W R/W R/W R/W 3 2 1 0 RMTS2 RMTS1 RMTS0 0 0 0 0 R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode.
PAGE 144
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access (Initial value) Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as DRAM interface.
PAGE 145
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE Description 0 BREQO output disabled. BREQO can be used as I/O port. 1 BREQO output enabled.
PAGE 146
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. 6.2.6 Bit 0 WAITE Description 0 Wait input by WAIT pin disabled. WAIT pin can be used as I/O port.
PAGE 147
Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit DRAM space, and 0 otherwise. Bit 4 CW2 Description 0 16-bit DRAM space selected 1 8-bit DRAM space selected (Initial value) Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface.
PAGE 148
6.2.7 DRAM Control Register (DRAMCR) Bit : 7 6 5 4 3 2 1 0 RFSHE RCW RMODE CMF CMIE CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode.
PAGE 149
Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared to 0.
PAGE 150
6.2.9 Bit Refresh Time Constant Register (RTCOR) : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a power-on reset and in hardware standby mode.
PAGE 151
6.3 Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 6-2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area.
PAGE 152
6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
PAGE 153
6.3.3 Memory Interfaces The H8S/2357 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area.
PAGE 154
6.3.5 Chip Select Signals The H8S/2357 Group can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6-3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset.
PAGE 155
6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
PAGE 156
16-Bit Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd.
PAGE 157
6.4.3 Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
PAGE 158
6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 T2 ø Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6-6 Bus Timing for 8-Bit 2-State Access Space Rev.6.00 Oct.28.
PAGE 159
8-Bit 3-State Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 ø Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6-7 Bus Timing for 8-Bit 3-State Access Space Rev.6.00 Oct.28.
PAGE 160
16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
PAGE 161
Bus cycle T1 T2 ø Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Oct.28.
PAGE 162
Bus cycle T1 T2 ø Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.6.00 Oct.28.
PAGE 163
16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
PAGE 164
Bus cycle T1 T2 T3 ø Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Oct.28.
PAGE 165
Bus cycle T1 T2 T3 ø Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.6.00 Oct.28.
PAGE 166
6.4.5 Wait Control When accessing external space, the H8S/2357 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL.
PAGE 167
Figure 6-14 shows an example of wait state insertion timing. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 ø WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Note: Write data indicates the timing of WAIT pin sampling. Figure 6-14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled.
PAGE 168
6.5 DRAM Interface 6.5.1 Overview When the H8S/2357 Group is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2357 Group. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode. 6.5.2 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH.
PAGE 169
6.5.5 Pins Used for DRAM Interface Table 6-7 shows the pins used for DRAM interfacing and their functions. Table 6-7 DRAM Interface Pins Pin With DRAM Setting Name I/O HWR WE Write enable Output When 2-CAS system is set, write enable for DRAM space access. LCAS LCAS Lower column address strobe Output Lower column address strobe for 16-bit DRAM space access CS2 RAS2 Row address strobe 2 Output Row address strobe when area 2 is designated as DRAM space.
PAGE 170
6.5.6 Basic Timing Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle.
PAGE 171
6.5.7 Precharge State Control When DRAM is accessed, RAS precharging time must be secured. With the H8S/2357 Series, one Tp state is always inserted when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit in MCR to 1. Set the appropriate number of T p cycles according to the DRAM connected and the operating frequency of the H8S/2357 Group. Figure 6-16 shows the timing when two Tp states are inserted.
PAGE 172
Figure 6-17 shows an example of wait state insertion timing. By program wait Tp Tr Tc1 Tw By WAIT pin Tw Tc2 ø WAIT Address bus CSn, (RAS) CAS Read Data bus Read data CAS Write Data bus Notes: Write data indicates the timing of WAIT pin sampling. n = 2 to 5 Figure 6-17 Example of Wait State Insertion Timing (CW2 = 1, 8-Bit Area Setting for Entire Space) Rev.6.00 Oct.28.
PAGE 173
6.5.9 Byte Access Control When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the control timing in the 2CAS system, and figure 6-19 shows an example 2-CAS system DRAM connection. When only DRAM with a ×8 configuration is connected, set the CW2 bit to 1 in MCR.
PAGE 174
6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1.
PAGE 175
RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. • RAS down mode To select RAS down mode, set the RCDM bit in MCR to 1.
PAGE 176
• RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6-22 shows an example of the timing in RAS up mode. In the case of burst ROM space access, the RAS signal is not restored to the high level.
PAGE 177
6.5.11 Refresh Control The H8S/2357 Group is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0.
PAGE 178
TRp TRr TRc1 TRc2 ø CS, (RAS) CAS, LCAS Note: n = 2 to 5 Figure 6-25 CBR Refresh Timing When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and RLW0. These bits are only enabled in refresh operations. Figure 6-26 shows the timing when the RCW bit is set to 1.
PAGE 179
TRp Software standby TRcr TRc3 ø CSn, (RAS) CAS, LCAS HWR, (WE) High Note: n = 2 to 5 Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0) 6.6 DMAC Single Address Mode and DRAM Interface When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed is selected. 6.6.
PAGE 180
6.6.2 When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the Tr state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space. Figure 6-29 shows the DACK output timing for the DRAM interface when DDS = 0.
PAGE 181
6.7.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR.
PAGE 182
Full access T1 T2 Burst access T1 T1 ø Only lower address changed Address bus CS0 AS RD Data bus Read data Read data Read data Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. Rev.6.00 Oct.
PAGE 183
6.8 Idle Cycle 6.8.1 Operation When the H8S/2357 Group accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on.
PAGE 184
(2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6-32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data.
PAGE 185
(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 633. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals.
PAGE 186
External read T1 T2 T3 DRAM space read Tp Tr Tc1 Tc2 ø Address bus RD Data bus Figure 6-34 Example of DRAM Access after External Read DRAM space read Tp Tr Tc1 External read Tc2 TI T1 T2 DRAM space read T3 TcI Tc1 Tc2 EXTAL Address RD RAS CAS, LCAS Data bus Idle cycle Figure 6-35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) DRAM space read Tp Tr Tc1 External read Tc2 TI T1 T2 DRAM space write T3 TcI Tc1 Tc2 EXTAL Address RD HWR RAS CAS, LCAS Data bus Idle
PAGE 187
6.8.3 Pin States in Idle Cycle Table 6-8 shows pin states in an idle cycle. Table 6-8 Pin States in Idle Cycle Pins Pin State A23 to A 0 Contents of next bus cycle D15 to D0 High impedance CSn* 2 High* 1 CAS High AS High RD High HWR High LWR DACKm* High 3 High Notes: 1. Remains low in DRAM space RAS down mode or a refresh cycle. 2. n = 0 to 7 3. m = 0, 1 Rev.6.00 Oct.28.
PAGE 188
6.9 Write Data Buffer Function The H8S/2357 Group has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 6-36 shows an example of the timing when the write data buffer function is used.
PAGE 189
6.10 Bus Release 6.10.1 Overview The H8S/2357 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request is generated, it can issue a bus request off-chip. 6.10.
PAGE 190
6.10.3 Pin States in External Bus Released State Table 6-9 shows pin states in the external bus released state. Table 6-9 Pin States in Bus Released State Pins Pin State A23 to A 0 High impedance D15 to D0 High impedance CSn* 1 High impedance CAS High impedance AS High impedance RD High impedance HWR High impedance LWR DACKm* Notes : 1. n = 0 to 7 2. m = 0, 1 Rev.6.00 Oct.28.
PAGE 191
6.10.4 Transition Timing Figure 6-37 shows the timing for transition to the bus-released state. CPU cycle T0 CPU cycle External bus released state T1 T2 ø High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO * Minimum 1 state [1] [2] [3] [4] [1] Low level of BREQ pin is sampled at rise of T2 state. [2] BACK pin is driven low at end of CPU read cycle, releasing bus to external [5] [6] bus master.
PAGE 192
6.11 Bus Arbitration 6.11.1 Overview The H8S/2357 Group has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
PAGE 193
6.11.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the bus arbiter transfers the bus to the bus master that issued the request.
PAGE 194
6.12 Resets and the Bus Controller In a power-on reset, the H8S/2357 Group, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset*, the bus controller’s registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored. Also, since the DMAC is initialized by a manual reset*, DACK and TEND output is disabled and these pins become I/O ports controlled by DDR and DR.
PAGE 195
Section 7 DMA Controller 7.1 Overview The H8S/2357 Group has a on-chip DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1.1 Features The features of the DMAC are listed below.
PAGE 196
7.1.2 Block Diagram A block diagram of the DMAC is shown in figure 7-1.
PAGE 197
7.1.3 Overview of Functions Tables 7-1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively.
PAGE 198
Table 7-1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination • • Auto-request 24 24 • External request • TPU channel 0 to 5 compare match/input capture A interrupts 24 24 • SCI transmission data empty interrupt • SCI reception data full interrupt • External request • A/D converter conversion end interrupt Normal mode Auto-request  Transfer request retained internally  Transfers continue for the specified
PAGE 199
7.1.4 Pin Configuration Table 7-2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output.
PAGE 200
7.1.5 Register Configuration Table 7-3 summarizes the DMAC registers.
PAGE 201
7.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7-4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0.
PAGE 202
7.2.
PAGE 203
7.2.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other.
PAGE 204
7.2.4 DMA Control Register (DMACR) Bit : 7 6 5 4 3 2 1 0 DMACR : DTSZ DTID5 RPE DTDIR DTF3 DTF2 DTF1 DTF0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in hardware standby mode. Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
PAGE 205
Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode.
PAGE 206
Channel B Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0 0 0 0 — 1 Activated by A/D converter conversion end interrupt 0 Activated by DREQ pin falling edge input* 1 Activated by DREQ pin low-level input 0 Activated by SCI channel 0 transmission data empty interrupt 1 Activated by SCI channel 0 reception data full interrupt 0 Activated by SCI channel 1 transmission data empty interrupt 1 Activated by SCI channel 1 reception data full interrupt 0 Activated by TPU channel 0
PAGE 207
7.2.
PAGE 208
Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. Bit 12 SAE0 Description 0 Transfer in dual address mode 1 Transfer in single address mode (Initial value) This bit is invalid in full address mode. Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting.
PAGE 209
Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting.
PAGE 210
Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A Description 0 Data transfer disabled 1 Data transfer enabled (Initial value) Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
PAGE 211
7.3 Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7-4. 7.3.
PAGE 212
(1) Normal Mode ETCRA Transfer Counter Bit : ETCR : Initial value : R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB ETCRB is not used in normal mode.
PAGE 213
7.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in hardware standby mode.
PAGE 214
Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area.
PAGE 215
• Block Transfer Mode Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0 0 0 0 — 1 Activated by A/D converter conversion end interrupt 0 Activated by DREQ pin falling edge input* 1 Activated by DREQ pin low-level input 0 Activated by SCI channel 0 transmission data empty interrupt 1 Activated by SCI channel 0 reception data full interrupt 0 Activated by SCI channel 1 transmission data empty interrupt 1 Activated by SCI channel 1 reception data full interrupt 0 Activated by TP
PAGE 216
7.3.5 DMA Band Control Register (DMABCR) Bit : 15 14 13 12 11 10 9 8 DMABCRH : FAE1 FAE0 — — DTA1 — DTA0 — Initial value : 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W Bit : 7 6 5 4 3 2 1 0 DMABCRL : DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
PAGE 217
Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC.
PAGE 218
Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1. Bit 7 DTME1 Description 0 Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt 1 Data transfer enabled (Initial value) Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0. Bit 5 DTME0 Description 0 Data transfer disabled.
PAGE 219
Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.
PAGE 220
7.4 Register Descriptions (3) 7.4.1 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC.
PAGE 221
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC.
PAGE 222
7.4.2 DMA Terminal Control Register (DMATCR) Bit : 7 6 5 4 3 2 1 0 DMATCR : — — TEE1 TEE0 — — — — Initial value : 0 0 0 0 0 0 0 0 R/W — — R/W R/W — — — — : DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in standby mode.
PAGE 223
7.4.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP15 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode.
PAGE 224
7.5 Operation 7.5.1 Transfer Modes Table 7-5 lists the DMAC modes.
PAGE 225
Operation in each mode is summarized below. (1) Sequential mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable.
PAGE 226
7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-6 summarizes register functions in sequential mode.
PAGE 227
Figure 7-3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID • (2DTSZ • (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7-3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
PAGE 228
Figure 7-4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Sequential mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
PAGE 229
7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-7 summarizes register functions in idle mode.
PAGE 230
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
PAGE 231
7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR.
PAGE 232
The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Figure 7-7 illustrates operation in repeat mode.
PAGE 233
Figure 7-8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Repeat mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL.
PAGE 234
7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR. Table 7-9 summarizes register functions in single address mode.
PAGE 235
Figure 7-9 illustrates operation in single address mode (when sequential mode is specified). Address T DACK Transfer 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID • (2DTSZ • (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7-9 Operation in Single Address Mode (When Sequential Mode Is Specified) Rev.6.00 Oct.28.
PAGE 236
Figure 7-10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR.
PAGE 237
7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB.
PAGE 238
Figure 7-11 illustrates operation in normal mode. Transfer Address TA Address BB Address BA Legend: Address TA Address TB Address BA Address BB Where : LA LB N Address TB = LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7-11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests.
PAGE 239
For setting details, see section 7.3.4, DMA Controller Register (DMACR). Figure 7-12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Normal mode setting Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA.
PAGE 240
7.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB.
PAGE 241
Address TB Address TA 1st block 2nd block Transfer Block area Address BB Consecutive transfer of M bytes or words is performed in response to one request Nth block Address BA Legend: Address TA Address TB Address BA Address BB Where : LA LB N M = LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (M•N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7-13 Operation in Block Transfer Mode (BLKDIR = 0) Rev.6.
PAGE 242
Figure 7-14 illustrates operation in block transfer mode when MARA is designated as a block area.
PAGE 243
Start (DTE = DTME = 1) Transfer request? No Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE·(–1)SAID·2DTSZ Write to address specified by MARB MARB = MARB + DAIDE·(–1)DAID ·2DTSZ ETCRAL = ETCRAL–1 ETCRAL = H'00 No Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 No Yes MARB = MARB – DAIDE·(–1)DAID·2DTSZ·ETCRAH MARA = MARA – SAIDE·(–1)SAID·2DTSZ·ETCRAH ETCRB = ETCRB – 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure 7-15 Operation Flow in Block Transfer Mode Transfer
PAGE 244
[1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Block transfer mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL.
PAGE 245
7.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7-12.
PAGE 246
Activation by External Request: If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin.
PAGE 247
When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a read strobe for the external device. Since there is no directional control for the external device, one or other of the above single directions should be used.
PAGE 248
7.5.10 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7-19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
PAGE 249
Full Address Mode (Cycle Steal Mode): Figure 7-20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
PAGE 250
Full Address Mode (Burst Mode): Figure 7-21 shows a transfer example in which TEND output is enabled and wordsize full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2state access space.
PAGE 251
Full Address Mode (Block Transfer Mode): Figure 7-22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
PAGE 252
DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-23 shows an example of DREQ pin falling edge activated normal mode transfer.
PAGE 253
Figure 7-24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
PAGE 254
DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-25 shows an example of DREQ level activated normal mode transfer.
PAGE 255
Figure 7-26 shows an example of DREQ level activated block transfer mode transfer.
PAGE 256
7.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 7-27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
PAGE 257
Single Address Mode (Write): Figure 7-29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
PAGE 258
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-31 shows an example of DREQ pin falling edge activated single address mode transfer.
PAGE 259
DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-32 shows an example of DREQ pin low level activated single address mode transfer.
PAGE 260
7.5.12 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
PAGE 261
DMA read DMA single CPU read DMA single CPU read ø Internal address Internal read signal External address RD DACK Figure 7-34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.
PAGE 262
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7-13. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer.
PAGE 263
7.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
PAGE 264
7.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7-37 shows the procedure for forcibly terminating DMAC operation by software. [1] Forced termination of DMAC Clear DTE bit to 0 Clear the DTE bit in DMABCRL to 0.
PAGE 265
7.5.17 Clearing Full Address Mode Figure 7-38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. Clearing full address mode Stop the channel [1] [1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0.
PAGE 266
7.6 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7-14 shows the interrupt sources and their priority order.
PAGE 267
7.7 Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
PAGE 268
(b) DMAC registers are read as shown in figure 7-41, when the DMAC transfer cycle occurs immediately after the DMAC register has been read. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write ø DMA internal address DMA control DMA register operation Idle Transfer source Transfer destination Read Write [1] Idle [2] Note: The lower word of MAR is the updated value after the operation in [1].
PAGE 269
(b) Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible.
PAGE 270
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1.
PAGE 271
Section 8 Data Transfer Controller 8.1 Overview The H8S/2357 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.
PAGE 272
8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
PAGE 273
8.1.3 Register Configuration Table 8-1 summarizes the DTC registers.
PAGE 274
8.2 Register Descriptions 8.2.1 DTC Mode Register A (MRA) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined — — — — — — — — MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.
PAGE 275
Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS Description 0 Destination side is repeat area or block area 1 Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. 8.2.
PAGE 276
8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 ––– 4 3 2 1 0 ––– Initial value : R/W : ––– Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — Unde- Unde- Unde- Unde- Undefined fined fined fined fined ––– — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.
PAGE 277
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 8.2.
PAGE 278
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1.
PAGE 279
8.3 Operation 8.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation.
PAGE 280
Table 8-2 DTC Functions Address Registers Transfer Mode Transfer Transfer Activation Source Source Destination • Normal mode • IRQ  One transfer request transfers one byte or one word • TPU TGI • 8-bit timer CMI  Memory addresses are incremented or decremented by 1 or 2 • SCI TXI or RXI • A/D converter ADI Repeat mode • DMAC DEND  One transfer request transfers one byte or one word • Software  Up to 65,536 transfers possible •  Memory addresses are incremented or decremented by
PAGE 281
8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared.
PAGE 282
8.3.3 DTC Vector Table Figure 8-4 shows the correspondence between DTC vector addresses and register information. Table 8-4 shows the correspondence between activation, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.
PAGE 283
Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Source Origin of Interrupt Source Vector Number Vector Address Write to DTVECR Software DTVECR IRQ0 External pin DTCE* Priority H'0400+ (DTVECR [6:0]<<1) — High 16 H'0420 DTCEA7 IRQ1 17 H'0422 DTCEA6 IRQ2 18 H'0424 DTCEA5 IRQ3 19 H'0426 DTCEA4 IRQ4 20 H'0428 DTCEA3 IRQ5 21 H'042A DTCEA2 IRQ6 22 H'042C DTCEA1 IRQ7 23 H'042E DTCEA0 ADI (A/D conversion end) A/D 28 H'0438 DTCEB
PAGE 284
Interrupt Source Origin of Interrupt Source TGI5B (GR5B compare match/ input capture) CMIA0 Vector Number Vector Address DTCE* Priority TPU channel 5 61 H'047A DTCED4 High 8-bit timer channel 0 64 H'0480 DTCED3 65 H'0482 DTCED2 68 H'0488 DTCED1 69 H'048A DTCED0 DMTEND0A (DMAC transfer end 0) DMAC 72 H'0490 DTCEE7 DMTEND0B (DMAC transfer end 1) 73 H'0492 DTCEE6 DMTEND1A (DMAC transfer end 2) 74 H'0494 DTCEE5 DMTEND1B (DMAC transfer end 3) 75 H'0496 DTCEE4 81 H'04A2
PAGE 285
DTC vector address Register information start address Register information Chain transfer Figure 8-4 Correspondence between DTC Vector Address and Register Information 8.3.4 Location of Register Information in Address Space Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address).
PAGE 286
8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode.
PAGE 287
8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0.
PAGE 288
8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested.
PAGE 289
8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer.
PAGE 290
8.3.9 Operation Timing Figures 8-10 to 8-12 show an example of DTC operation timing.
PAGE 291
ø DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer Transfer information information write read Transfer information write Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status.
PAGE 292
The number of execution states is calculated from the formula below. Note that Σ means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL ) + M · SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states.
PAGE 293
[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception data full (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC.
PAGE 294
[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0).
PAGE 295
Section 9 I/O Ports 9.1 Overview The H8S/2357 Group has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port 4). Table 9-1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
PAGE 296
Table 9-1 Port Functions Port Description Port 1 • 8-bit I/O port Pins Mode 4*3 Mode 5*3 Mode 6 Mode 7 P17/PO15/TIOCB2/TCLKD 8-bit I/O port also functioning as DMA controller output pins (DACK0 and DACK1), TPU I/O pins (TCLKA, TCLKB, P16/PO14/TIOCA2 TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, P15/PO13/TIOCB1/TCLKC TIOCA1, TIOCB1, TIOCA2, TIOCB2) and PPG output pins P14/PO12/TIOCA1 (PO15 to PO8) P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0/DACK1 P10/PO8/TIOCA0/DACK0 Port 2 • 8-bit I/O
PAGE 297
Port Description Pins Port A • 8-bit I/O PA 7/A 23 /IRQ7 port PA 6/A 22 /IRQ6 • On-chip PA 5/A 21 /IRQ5 MOS input 4 pull-up* • Open-drain output capability*4 • SchmittPA 4/A 20 /IRQ4 triggered input (PA4 to PA7) PA 3/A 19 to PA0/A 16 Mode 4*3 Mode 5*3 When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ5) When DDR = 1: address output Mode 6 Mode 7 When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ4) Dual function
PAGE 298
Port Description Port F • 8-bit I/O port Pins PF7/ø Mode 4*3 Mode 5*3 Mode 6 When DDR = 0: input port When DDR = 1 (after reset): ø output Mode 7 When DDR = 0 (after reset): input port When DDR = 1: ø output PF6/AS AS, RD, HWR, LWR output I/O port PF5/RD PF4/HWR PF3/LWR PF2/LCAS/WAIT/BREQO When WAITE = 0 and BREQOE = 0 (after reset): I/O port When WAITE = 1 and BREQOE = 0: WAIT input When WAITE = 0 and BREQOE = 1: BREQO output When RMTS2 to RMTS0= B'001 to B'011, CW2= 0, and LCASS= 0: LCAS output
PAGE 299
9.2 Port 1 9.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC output pins (DACK0 and DACK1). Port 1 pin functions are the same in all operating modes. Figure 9-1 shows the port 1 pin configuration.
PAGE 300
Port 1 Data Direction Register (P1DDR) Bit : 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin.
PAGE 301
9.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC output pins (DACK0 and DACK1). Port 1 pin functions are shown in table 9-3.
PAGE 302
Pin Selection Method and Pin Functions P16/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bit NDER14 in NDERH, and bit P16DDR. TPU Channel 2 Setting Table Below (1) Table Below (2) P16DDR — 0 1 1 NDER14 — — 0 1 TIOCA2 output P16 input P16 output PO14 output Pin function TIOCA2 input * 1 Note: 1.
PAGE 303
Pin Selection Method and Pin Functions P15/PO13/TIOCB1/ The pin function is switched as shown below according to the combination of TCLKC the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
PAGE 304
Pin Selection Method and Pin Functions P14/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bit NDER12 in NDERH, and bit P14DDR. TPU Channel 1 Setting Table Below (1) Table Below (2) P14DDR — 0 1 1 NDER12 — — 0 1 TIOCA1 output P14 input P14 output PO12 output Pin function TIOCA1 input * 1 Note: 1.
PAGE 305
Pin Selection Method and Pin Functions P13/PO11/TIOCD0/ The pin function is switched as shown below according to the combination of TCLKB the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR.
PAGE 306
Pin Selection Method and Pin Functions P12/PO10/TIOCC0/ The pin function is switched as shown below according to the combination of TCLKA the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.
PAGE 307
Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ The pin function is switched as shown below according to the combination of DACK1 the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, bit NDER9 in NDERH, bit SAE1 in DMABCRH, and bit P11DDR.
PAGE 308
Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ The pin function is switched as shown below according to the combination of DACK0 the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, bit NDER8 in NDERH, bit SAE0 in DMABCRH, and bit P10DDR.
PAGE 309
9.3 Port 2 9.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as PPG output pins (PO7 to PO0), TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 9-2 shows the port 2 pin configuration.
PAGE 310
P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode. As the PPG, TPU, and 8-bit timer are initialized by a manual reset*, the pin states are determined by the P2DDR and P2DR specifications. Note: * Manual reset is only supported in the H8S/2357 ZTAT.
PAGE 311
9.3.3 Pin Functions Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are shown in table 9-5.
PAGE 312
Pin Selection Method and Pin Functions P26/PO6/TIOCA5/ The pin function is switched as shown below according to the combination of TMO0 the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bit NDER6 in NDERL, bits OS3 to OS0 in TCSR0, and bit P26DDR.
PAGE 313
Pin Selection Method and Pin Functions P25/PO5/TIOCB4/ This pin is used as the 8-bit timer external clock input pin when external clock TMCI1 is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4 and bits IOB3 to IOB0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, bit NDER5 in NDERL, and bit P25DDR.
PAGE 314
Pin Selection Method and Pin Functions P24/PO4/TIOCA4/ This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and TMRI1 CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, bit NDER4 in NDERL, and bit P24DDR.
PAGE 315
Pin Selection Method and Pin Functions P23/PO3/TIOCD3/ This pin is used as the 8-bit timer external clock input pin when external clock TMCI0 is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, bit NDER3 in NDERL, and bit P23DDR.
PAGE 316
Pin Selection Method and Pin Functions P22/PO2/TIOCC3/ This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and TMRI0 CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, bit NDER2 in NDERL, and bit P22DDR.
PAGE 317
Pin Selection Method and Pin Functions P21/PO1/TIOCB3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, bit NDER1 in NDERL, and bit P21DDR.
PAGE 318
Pin Selection Method and Pin Functions P20/PO0/TIOCA3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, bit NDER0 in NDERL, and bit P20DDR. TPU Channel 3 Setting Table Below (1) Table Below (2) P20DDR — 0 1 1 NDER0 — — 0 1 TIOCA3 output P20 input P20 output PO0 output Pin function TIOCA3 input * 1 Note: 1.
PAGE 319
9.4 Port 3 9.4.1 Overview Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are the same in all operating modes. Figure 9-3 shows the port 3 pin configuration. Port 3 pins P35 (I/O)/ SCK1 (I/O) P34 (I/O)/ SCK0 (I/O) P33 (I/O)/ RxD1 (input) Port 3 P32 (I/O)/ RxD0 (input) P31 (I/O)/ TxD1 (output) P30 (I/O)/ TxD0 (output) Figure 9-3 Port 3 Pin Functions 9.4.
PAGE 320
P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and P3DR specifications. Note: * Manual reset is only supported in the H8S/2357 ZTAT.
PAGE 321
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. P3ODR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. 9.4.
PAGE 322
Pin Selection Method and Pin Functions P33/RxD1 The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE P33DDR Pin function 0 1 0 1 — P33 input pin P33 output pin* RxD1 input pin Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output. P32/RxD0 The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR.
PAGE 323
9.5 Port 4 9.5.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 9-4 shows the port 4 pin configuration.
PAGE 324
9.6 Port 5 9.6.1 Overview Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2) and the A/D converter input pin (ADTRG). Port 5 pin functions are the same in all operating modes. Figure 9-5 shows the port 5 pin configuration. Port 5 pins P53 (I/O)/ADTRG (input) P52 (I/O)/SCK2 (I/O) Port 5 P51 (I/O)/RxD2 (input) P50 (I/O)/TxD2 (output) Figure 9-5 Port 5 Pin Functions 9.6.2 Register Configuration Table 9-9 shows the port 5 register configuration.
PAGE 325
Note: * Manual reset is only supported in the H8S/2357 ZTAT. Port 5 Data Register (P5DR) Bit : 7 6 5 4 3 2 1 0 — — — — P53DR P52DR P51DR P50DR Initial value : Undefined Undefined Undefined Undefined R/W : — — — — 0 0 0 0 R/W R/W R/W R/W P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P53 to P50). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PAGE 326
9.6.3 Pin Functions Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2), and the A/D converter input pin (ADTRG). Port 5 pin functions are shown in table 9-10. Table 9-10 Port 5 Pin Functions Pin Selection Method and Pin Functions P53/ADTRG The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 in the A/D converter ADCR, and bit P53DDR.
PAGE 327
9.7 Port 6 9.7.1 Overview Port 6 is an 8-bit I/O port. Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). The functions of pins P65 to P62 are the same in all operating modes, while the functions of pins P6 7, P6 6, P6 1, and P60 change according to the operating mode. Pins P67 to P6 4 are schmitt-triggered inputs. Figure 9-6 shows the port 6 pin configuration.
PAGE 328
Port 6 Data Direction Register (P6DDR) Bit : 7 6 5 4 3 2 1 0 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin.
PAGE 329
9.7.3 Pin Functions Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). Port 6 pin functions are shown in table 9-12. Table 9-12 Port 6 Pin Functions Pin Selection Method and Pin Functions P67/IRQ3/CS7 The pin function is switched as shown below according to bit P67DDR.
PAGE 330
Pin Selection Method and Pin Functions P63/TEND1 The pin function is switched as shown below according to the combination of bit TEE1 in the DMAC DMATCR, and bit P63DDR. TEE1 0 P63DDR Pin function P62/DREQ1 1 0 1 — P63 input pin P63 output pin TEND1 output The pin function is switched as shown below according to bit P62DDR.
PAGE 331
9.8 Port A 9.8.1 Overview Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and interrupt input pins (IRQ4 to IRQ7). The pin functions change according to the operating mode. Port A has a on-chip MOS input pull-up function that can be controlled by software. Pins PA7 to PA4 are schmitt-triggered inputs. Figure 9-7 shows the port A pin configuration.
PAGE 332
9.8.2 Register Configuration Table 9-13 shows the port A register configuration. Table 9-13 Port A Registers Name Abbreviation R/W Initial Value Address* 1 Port A data direction register PADDR W H'00 H'FEB9 Port A data register PADR R/W H'00 H'FF69 PORTA R Undefined H'FF59 R/W H'00 H'FF70 R/W H'00 H'FF77 Port A register 2 Port A MOS pull-up control register* PAPCR Port A open-drain control register* 2 PAODR Notes: 1. Lower 16 bits of the address. 2.
PAGE 333
Port A Data Register (PADR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA 0). PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode.
PAGE 334
Port A Open Drain Control Register (PAODR) (On-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA7 to PA0). All bits are valid in mode 7.
PAGE 335
Mode 6 (On-Chip ROM Version Only): In mode 6, port A pins function as address outputs or input ports and interrupt input pins. Input or output can be specified on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Port A pin functions in mode 6 are shown in figure 9-9.
PAGE 336
9.8.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) Port A has a on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used by pins PA7 to PA5 in modes 4 and 5, and by all pins in modes 6 and 7. MOS input pull-up can be specified as on or off on an individual bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin.
PAGE 337
9.9 Port B 9.9.1 Overview Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a on-chip MOS input pull-up function that can be controlled by software (on-chip ROM version only). Figure 9-11 shows the port B pin configuration.
PAGE 338
9.9.2 Register Configuration (On-Chip ROM Version Only) Table 9-15 shows the port B register configuration. Table 9-15 Port B Registers Name Abbreviation R/W Initial Value Address * Port B data direction register PBDDR W H'00 H'FEBA Port B data register PBDR R/W H'00 H'FF6A Port B register PORTB R Undefined H'FF5A Port B MOS pull-up control register PBPCR R/W H'00 H'FF71 Note: * Lower 16 bits of the address.
PAGE 339
Note: * Manual reset is only supported in the H8S/2357 ZTAT. Port B Register (PORTB) (On-Chip ROM Version Only) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 —* —* —* —* —* —* —* —* R R R R R R R R Note: * Determined by state of pins PB7 to PB 0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR.
PAGE 340
9.9.3 Pin Functions Mode 7 (On-Chip ROM Version Only): In mode 7, port B pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Port B pin functions in mode 7 are shown in figure 9-12.
PAGE 341
Modes 4 and 5: In modes 4 and 5, port B pins are automatically designated as address outputs. Port B pin functions in modes 4 and 5 are shown in figure 9-14. A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Figure 9-14 Port B Pin Functions (Modes 4 and 5) 9.9.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) Port B has a on-chip MOS input pull-up function that can be controlled by software.
PAGE 342
9.10 Port C 9.10.1 Overview Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a on-chip MOS input pull-up function that can be controlled by software (on-chip ROM version only). Figure 9-15 shows the port C pin configuration.
PAGE 343
9.10.2 Register Configuration (On-Chip ROM Version Only) Table 9-17 shows the port C register configuration. Table 9-17 Port C Registers Name Abbreviation R/W Initial Value Address * Port C data direction register PCDDR W H'00 H'FEBB Port C data register PCDR R/W H'00 H'FF6B Port C register PORTC R Undefined H'FF5B Port C MOS pull-up control register PCPCR R/W H'00 H'FF72 Note: * Lower 16 bits of the address.
PAGE 344
Note: * Manual reset is only supported in the H8S/2357 ZTAT. Port C Register (PORTC) (On-Chip ROM Version Only) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 —* —* —* —* —* —* —* —* R R R R R R R R Note: * Determined by state of pins PC 7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR.
PAGE 345
9.10.3 Pin Functions Mode 7 (On-Chip ROM Version Only): In mode 7, port C pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Port C pin functions in mode 7 are shown in figure 9-16.
PAGE 346
Modes 4 and 5: In modes 4 and 5, port C pins are automatically designated as address outputs. Port C pin functions in modes 4 and 5 are shown in figure 9-18. A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 9-18 Port C Pin Functions (Modes 4 and 5) 9.10.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) Port C has a on-chip MOS input pull-up function that can be controlled by software.
PAGE 347
9.11 Port D 9.11.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. In the H8S/2352, port D pins are dedicated data bus pins. Port D has a on-chip MOS input pull-up function that can be controlled by software (on-chip ROM version only). Figure 9-19 shows the port D pin configuration.
PAGE 348
9.11.2 Register Configuration (On-Chip ROM Version Only) Table 9-19 shows the port D register configuration. Table 9-19 Port D Registers Name Abbreviation R/W Initial Value Address * Port D data direction register PDDDR W H'00 H'FEBC Port D data register PDDR R/W H'00 H'FF6C Port D register PORTD R Undefined H'FF5C Port D MOS pull-up control register PDPCR R/W H'00 H'FF73 Note: * Lower 16 bits of the address.
PAGE 349
Port D Register (PORTD) (On-Chip ROM Version Only) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 —* —* —* —* —* —* —* —* R R R R R R R R Note: * Determined by state of pins PD 7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD 0) must always be performed on PDDR.
PAGE 350
9.11.3 Pin Functions Modes 7 (On-Chip ROM Version Only): In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Port D pin functions in mode 7 are shown in figure 9-20.
PAGE 351
9.11.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) Port D has a on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode.
PAGE 352
9.12 Port E 9.12.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a on-chip MOS input pull-up function that can be controlled by software (on-chip ROM version only). Figure 9-22 shows the port E pin configuration.
PAGE 353
9.12.2 Register Configuration Table 9-21 shows the port E register configuration. Table 9-21 Port E Registers Name Abbreviation R/W Initial Value Address* 1 Port E data direction register PEDDR W H'00 H'FEBD Port E data register PEDR R/W H'00 H'FF6D Port E register PORTE R Undefined H'FF5D Port E MOS pull-up control register* 2 PEPCR R/W H'00 H'FF74 2 1 Notes: 1. Lower 16 bits of the address. 2. PEPCR settings are prohibited in the ROMless version.
PAGE 354
PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Port E Register (PORTE) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 —* —* —* —* —* —* —* —* R R R R R R R R Note: * Determined by state of pins PE 7 to PE 0. PORTE is an 8-bit read-only register that shows the pin states.
PAGE 355
9.12.3 Pin Functions Mode 7*: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. Note: * Modes 6 and 7 are provided in the on-chip ROM version only. Port E pin functions in mode 7 are shown in figure 9-23.
PAGE 356
9.12.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) Port E has a on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in mode 4, 5, or 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin.
PAGE 357
9.13 Port F 9.13.1 Overview Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin. Figure 9-25 shows the port F pin configuration.
PAGE 358
9.13.2 Register Configuration Table 9-23 shows the port F register configuration. Table 9-23 Port F Registers Name Abbreviation R/W Initial Value Address * 1 Port F data direction register PFDDR W H'80/H'00* 2 H'FEBE Port F data register PFDR R/W H'00 H'FF6E Port F register PORTF R Undefined H'FF5E Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode.
PAGE 359
Port F Data Register (PFDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode.
PAGE 360
9.13.3 Pin Functions Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin. The pin functions differ between modes 4 to 6, and mode 7. Port F pin functions are shown in table 9-24. Table 9-24 Port F Pin Functions Pin Selection Method and Pin Functions PF 7/ø The pin function is switched as shown below according to bit PF7DDR.
PAGE 361
Pin Selection Method and Pin Functions PF 2/LCAS/WAIT/ BREQO The pin function is switched as shown below according to the combination of the operating mode, and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE, ABW5 to ABW2, and PF2DDR. Operating Mode Modes 4 to 6* 2 LCASS 0* 1 BREQOE — 1 — 0 WAITE — PF2DDR — 0 1 LCAS output pin PF 2 input pin PF 2 output pin Pin function Mode 7* 2 0 1 1 — — — — — WAIT BREQO input output pin pin 0 1 PF 2 input pin PF 2 output pin Note: 1.
PAGE 362
9.14 Port G 9.14.1 Overview Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). Figure 9-26 shows the port G pin configuration.
PAGE 363
Port G Data Direction Register (PGDDR) Bit : 7 6 5 — — — 4 3 2 1 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Modes 6, 7 Initial value : Undefined Undefined Undefined 0 0 0 0 0 R/W W W W W W Initial value : Undefined Undefined Undefined 1 0 0 0 0 R/W W W W W W : — — — Modes 4, 5 : — — — PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved.
PAGE 364
Port G Register (PORTG) Bit : 7 6 5 4 3 2 1 0 — — — PG4 PG3 PG2 PG1 PG0 —* —* —* —* —* R R R R R Initial value : Undefined Undefined Undefined R/W : — — — Note: * Determined by state of pins PG4 to PG 0. PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port G pins (PG4 to PG 0) must always be performed on PGDR. Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PAGE 365
9.14.3 Pin Functions Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). The pin functions are different in mode 7, and modes 4 to 6. Port G pin functions are shown in table 9-26. Table 9-26 Port G Pin Functions Pin Selection Method and Pin Functions PG4/CS0 The pin function is switched as shown below according to the operating mode and bit PG4DDR.
PAGE 366
Rev.6.00 Oct.28.
PAGE 367
Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview The H8S/2357 Group has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 10.1.
PAGE 368
• A/D converter conversion start trigger can be generated  Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger • Module stop mode can be set  As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode. Table 10-1 lists the functions of the TPU. Rev.6.00 Oct.28.
PAGE 369
Table 10-1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock ø/1 ø/4 ø/16 ø/64 TCLKA TCLKB TCLKC TCLKD ø/1 ø/4 ø/16 ø/64 ø/256 TCLKA TCLKB ø/1 ø/4 ø/16 ø/64 ø/1024 TCLKA TCLKB TCLKC ø/1 ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096 TCLKA ø/1 ø/4 ø/16 ø/64 ø/1024 TCLKA TCLKC ø/1 ø/4 ø/16 ø/64 ø/256 TCLKA TCLKC TCLKD General registers TGR0A TGR0B TGR1A TGR1B TGR2A TGR2B TGR3A TGR3B TGR4A TGR4B TGR5A TGR5B General registers/ buffer registers TGR0C TGR0D — — TGR3
PAGE 370
Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DMAC TGR0A activation compare match or input capture TGR1A compare match or input capture TGR2A compare match or input capture TGR3A compare match or input capture TGR4A compare match or input capture TGR5A compare match or input capture DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture T
PAGE 371
10.1.
PAGE 372
10.1.3 Pin Configuration Table 10-2 summarizes the TPU pins.
PAGE 373
10.1.4 Register Configuration Table 10-3 summarizes the TPU registers.
PAGE 374
Channel Name Abbreviation R/W Initial Value Address* 1 3 Timer control register 3 TCR3 R/W H'00 H'FE80 Timer mode register 3 TMDR3 R/W H'C0 H'FE81 Timer I/O control register 3H TIOR3H R/W H'00 H'FE82 Timer I/O control register 3L TIOR3L R/W H'00 H'FE83 H'40 H'FE84 H'C0 H'FE85 Timer interrupt enable register 3 TIER3 4 5 All R/W 2 Timer status register 3 TSR3 R/(W)* Timer counter 3 TCNT3 R/W H'0000 H'FE86 Timer general register 3A TGR3A R/W H'FFFF H'FE88 Timer g
PAGE 375
10.2 Register Descriptions 10.2.
PAGE 376
Bits 7 to 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source.
PAGE 377
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
PAGE 378
Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on ø/1 1 Internal clock: counts on ø/4 0 Internal clock: counts on ø/16 1 Internal clock: counts on ø/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on ø/256 1 Counts on TCNT2 overflow/underflow 1 1 0 1 (Initial value) Note: This setting is ignored when channel 1 is in phase counting mode.
PAGE 379
Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 4 0 0 0 Internal clock: counts on ø/1 1 Internal clock: counts on ø/4 0 Internal clock: counts on ø/16 1 Internal clock: counts on ø/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 0 Internal clock: counts on ø/1024 1 Counts on TCNT5 overflow/underflow 1 1 0 1 (Initial value) Note: This setting is ignored when channel 4 is in phase counting mode.
PAGE 380
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. TMDR register settings should be made only when TCNT operation is stopped. Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
PAGE 381
10.2.
PAGE 382
Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD.
PAGE 383
Channel Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 0 0 1 1 0 TGR0D is Output disabled output Initial output is 0 compare output 2 register* 0 0 Output disabled 1 1 0 Initial output is 1 output 1 1 0 0 0 1 1 1 × × × 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR0D is Capture input source is input TIOCD0 pin capture regis
PAGE 384
Channel Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 2 0 0 0 0 1 1 0 TGR2B is Output disabled output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 × 0 0 1 1 × 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR2B is Capture input source is input TIOCB2 pin capture register Input
PAGE 385
Channel Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 Description 3 0 0 0 0 1 1 0 TGR3D is Output disabled output Initial output is 0 compare output 2 register* 0 0 Output disabled 1 1 0 Initial output is 1 output 1 1 0 0 0 1 1 1 × × × 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR3D is Capture input source is input TIOCD3 pin capture regis
PAGE 386
Channel Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 4 0 0 0 0 1 1 0 TGR4B is Output disabled output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR4B is Capture input source is input TIOCB4 pin capture register
PAGE 387
Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC.
PAGE 388
Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 1 0 0 0 0 1 1 0 TGR1A is Output disabled output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is Capture input source is input TIOCA1 pin capture registe
PAGE 389
Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 3 0 0 0 0 1 1 0 TGR3A is Output disabled output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR3A is Capture input source is input TIOCA3 pin capture registe
PAGE 390
Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 4 0 0 0 0 1 1 0 TGR4A is Output disabled output Initial output is 0 compare output register 0 0 Output disabled 1 1 0 Initial output is 1 output 1 1 0 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR4A is Capture input source is input TIOCA4 pin capture register
PAGE 391
10.2.
PAGE 392
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4 TCIEV Description 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled (Initial value) Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved.
PAGE 393
10.2.5 Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 Bit : 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 R/W — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* : Note: * Can only be written with 0 for flag clearing.
PAGE 394
Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV 0 Description [Clearing condition] (Initial value) When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved.
PAGE 395
Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match.
PAGE 396
10.2.
PAGE 397
Bits 7 and 6—Reserved: Should always be written with 0. Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn Description 0 TCNTn count operation is stopped 1 TCNTn performs count operation (Initial value) n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained.
PAGE 398
10.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP13 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode.
PAGE 399
10.3 Interface to Bus Master 10.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10-2.
PAGE 400
10.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 10-3 to 10-5.
PAGE 401
10.4 Operation 10.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting.
PAGE 402
10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 10-6 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
PAGE 403
• Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
PAGE 404
Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. • Example of setting procedure for waveform output by compare match Figure 10-9 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR.
PAGE 405
Figure 10-11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B.
PAGE 406
• Example of input capture operation Figure 10-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
PAGE 407
10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
PAGE 408
For details of PWM modes, see section 10.4.6, PWM Modes. Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A Time H'0000 TIOC0A TIOC1A TIOC2A Figure 10-15 Example of Synchronous Operation Rev.6.00 Oct.28.
PAGE 409
10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10-5 shows the register combinations used in buffer operation.
PAGE 410
Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. Set buffer operation [2] [3] Set the CST bit in TSTR to 1 to start the count operation.
PAGE 411
• When TGR is an input capture register Figure 10-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
PAGE 412
10.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10-6 shows the register combinations used in cascaded operation.
PAGE 413
Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
PAGE 414
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs.
PAGE 415
Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
PAGE 416
Figure 10-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty.
PAGE 417
Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
PAGE 418
10.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
PAGE 419
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-29 Example of Phase Counting Mode 1 Operation Table 10-9 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) High level Operation Up-count Low level Low level High level High level Down-count Low level High level Low level Legend: : Rising edge : Falling edge
PAGE 420
Table 10-10 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation High level Don’t care Low level Don’t care Low level Don’t care High level Up-count High level Don’t care Low level Don’t care High level Don’t care Low level Down-count Legend: : Rising edge : Falling edge • Phase counting mode 3 Figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11 summarize
PAGE 421
Table 10-11 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation High level Don’t care Low level Don’t care Low level Don’t care High level Up-count High level Down-count Low level Don’t care High level Don’t care Low level Don’t care Legend: : Rising edge : Falling edge • Phase counting mode 4 Figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12 summarize
PAGE 422
Table 10-12 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) High level Operation Up-count Low level Low level Don’t care High level High level Down-count Low level High level Don’t care Low level Legend: : Rising edge : Falling edge Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel
PAGE 423
Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 + TGR0A (speed control period) – + TGR0C (position control period) – TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10-33 Phase Counting Mode Application Example Rev.6.00 Oct.28.
PAGE 424
10.5 Interrupts 10.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
PAGE 425
Table 10-13 TPU Interrupts Channel Interrupt Source Description 0 TGI0A TGR0A input capture/compare match Possible TGI0B TGR0B input capture/compare match Not possible Possible TGI0C TGR0C input capture/compare match Not possible Possible TGI0D TGR0D input capture/compare match Not possible Possible TCI0V TCNT0 overflow TGI1A TGR1A input capture/compare match Possible TGI1B TGR1B input capture/compare match Not possible Possible TCI1V TCNT1 overflow Not possible Not possible TCI1U TCNT1
PAGE 426
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
PAGE 427
10.6 Operation Timing 10.6.1 Input/Output Timing TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and figure 10-35 shows TCNT count timing in external clock operation. ø Internal clock Falling edge Rising edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 10-34 Count Timing in Internal Clock Operation ø External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 10-35 Count Timing in External Clock Operation Rev.
PAGE 428
Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10-36 shows output compare output timing.
PAGE 429
ø Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 10-38 Counter Clear Timing (Compare Match) ø Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 10-39 Counter Clear Timing (Input Capture) Rev.6.00 Oct.28.
PAGE 430
Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation. ø n TCNT n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 10-40 Buffer Operation Timing (Compare Match) ø Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 10-41 Buffer Operation Timing (Input Capture) Rev.6.00 Oct.28.
PAGE 431
10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing.
PAGE 432
TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
PAGE 433
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag clearing by the DTC or DMAC.
PAGE 434
10.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.
PAGE 435
Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10-49 shows the timing in this case.
PAGE 436
Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10-51 shows the timing in this case.
PAGE 437
Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10-53 shows the timing in this case.
PAGE 438
Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10-55 shows the timing in this case.
PAGE 439
Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10-57 shows the operation timing when there is contention between TCNT write and overflow.
PAGE 440
Rev.6.00 Oct.28.
PAGE 441
Section 11 Programmable Pulse Generator (PPG) 11.1 Overview The H8S/2357 Group has a on-chip programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate both simultaneously and independently. 11.1.1 Features PPG features are listed below.
PAGE 442
11.1.2 Block Diagram Figure 11-1 shows a block diagram of the PPG.
PAGE 443
11.1.3 Pin Configuration Table 11-1 summarizes the PPG pins.
PAGE 444
11.1.4 Registers Table 11-2 summarizes the PPG registers.
PAGE 445
11.2 Register Descriptions 11.2.
PAGE 446
11.2.
PAGE 447
Address H'FF4E Bit : 7 6 5 4 3 2 1 0 — — — — — — — — Initial value : 1 1 1 1 1 1 1 1 R/W — — — — — — — — : If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address is H'FF4D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FF4F consists entirely of reserved bits that cannot be modified and are always read as 1.
PAGE 448
Address H'FF4D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 — — — — 0 0 0 0 1 1 1 1 R/W R/W R/W R/W — — — — 7 6 5 4 3 2 1 0 — — — — NDR3 NDR2 NDR1 NDR0 Initial value : 1 1 1 1 0 0 0 0 R/W — — — — R/W R/W R/W R/W 4 3 2 1 0 Initial value : R/W : Address H'FF4F Bit 11.2.
PAGE 449
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4).
PAGE 450
Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output group 2 (pins PO11 to PO8). Bit 6 G2INV Description 0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH) 1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH) (Initial value) Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4).
PAGE 451
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4).
PAGE 452
11.2.9 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP11 bit in MSTPCR is set to 1, PPG operation stops at the end of the bus cycle and a transition is made to module stop mode.
PAGE 453
11.3 Operation 11.3.1 Overview PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating conditions.
PAGE 454
11.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø N TCNT TGRA N+1 N Compare match A signal n NDRH PODRH PO8 to PO15 m n m n Figure 11-3 Timing of Transfer and Output of NDR Contents (Example) Rev.6.00 Oct.28.
PAGE 455
11.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for setting up normal pulse output.
PAGE 456
Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output.
PAGE 457
[1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled) Non-overlapping PPG output Select TGR functions [1] Set TGR values [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] TPU setup PPG setup TPU setup Enable pulse output [6] Select output trigger [7] Set non-overlapping groups [8] Set next pulse output data [9] Start counter [10] Compare match A? No [3] Select the counter clock source with bits TPSC2 to TPSC0 in
PAGE 458
Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output): Figure 11-7 shows an example in which pulse output is used for four-phase complementary non-overlapping pulse output.
PAGE 459
11.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11-7. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRL Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11-8 Inverted Pulse Output (Example) Rev.6.00 Oct.28.
PAGE 460
11.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11-9 shows the timing of this output. ø TIOC pin Input capture signal NDR N PODR M PO M N N Figure 11-9 Pulse Output Triggered by Input Capture (Example) Rev.6.00 Oct.28.
PAGE 461
11.4 Usage Notes Operation of Pulse Output Pins: Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur.
PAGE 462
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs.
PAGE 463
Section 12 8-Bit Timers 12.1 Overview The H8S/2357 Group includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 12.1.1 Features The features of the 8-bit timer module are listed below.
PAGE 464
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the 8-bit timer module.
PAGE 465
12.1.3 Pin Configuration Table 12-1 summarizes the input and output pins of the 8-bit timer.
PAGE 466
12.2 Register Descriptions 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) TCNT0 Bit TCNT1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. This clock source is selected by clock select bits CKS2 to CKS0 of TCR.
PAGE 467
12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) TCORB0 Bit TCORB1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. TCORB is continually compared with the value in TCNT.
PAGE 468
Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag of TCSR is set to 1. Bit 5 OVIE Description 0 OVF interrupt requests (OVI) are disabled 1 OVF interrupt requests (OVI) are enabled (Initial value) Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by which TCNT is cleared: by compare match A or B, or by an external reset input.
PAGE 469
12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1) TCSR0 Bit : 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 0 0 0 0 0 0 0 0 : R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W : 7 6 5 4 3 2 1 0 CMFB CMFA OVF — OS3 OS2 OS1 OS0 Initial value : R/W TCSR1 Bit Initial value : R/W : 0 0 0 1 0 0 0 0 R/(W)* R/(W)* R/(W)* — R/W R/W R/W R/W Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
PAGE 470
Bit 5—Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00). Bit 5 OVF Description 0 [Clearing condition] (Initial value) Cleared by reading OVF when OVF = 1, then writing 0 to OVF 1 [Setting condition] Set when TCNT overflows from H'FF to H'00 Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare-match A. In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified.
PAGE 471
12.2.6 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode.
PAGE 472
12.3 Operation 12.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (ø/8, ø/64, or ø/8192) divided from the system clock (ø) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 12-2 shows the count timing.
PAGE 473
12.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 12-4 shows this timing.
PAGE 474
12.3.3 Timing of External RESET on TCNT TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12-7 shows the timing of this operation. ø External reset input pin Clear signal TCNT N–1 N H'00 Figure 12-7 Timing of External Reset 12.3.4 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00).
PAGE 475
12.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below.
PAGE 476
12.4 Interrupts 12.4.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 12-3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts.
PAGE 477
12.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12-9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match.
PAGE 478
12.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12-10 shows this operation.
PAGE 479
12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12-11 shows this operation. TCNT write cycle by CPU T1 T2 ø Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12-11 Contention between TCNT Write and Increment Rev.6.00 Oct.28.
PAGE 480
12.6.3 Contention between TCOR Write and Compare Match During the T 2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a compare match event occurs. Figure 12-12 shows this operation. TCOR write cycle by CPU T1 T2 ø Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Prohibited Figure 12-12 Contention between TCOR Write and Compare Match 12.6.
PAGE 481
12.6.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12-5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected.
PAGE 482
No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. 12.6.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
PAGE 483
Section 13 Watchdog Timer 13.1 Overview The H8S/2357 Group has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2357 Group. When this watchdog function is not needed, the WDT can be used as an interval timer.
PAGE 484
13.1.2 Block Diagram Figure 13-1 shows a block diagram of the WDT. Overflow Clock WDTOVF*2 Internal reset Clock select Reset control signal*1 RSTCSR ø/2 ø/64 ø/128 ø/512 ø/2048 ø/8192 ø/32768 ø/131072 Internal clock sources TCNT TSCR Module bus Bus interface Internal bus WOVI (interrupt request signal) Interrupt control WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Notes: 1.
PAGE 485
13.1.4 Register Configuration The WDT has three registers, as summarized in table 13-2. These registers control clock selection, WDT mode switching, and the reset signal. Table 13-2 WDT Registers Address* 1 Name Abbreviation R/W Timer control/status register TCSR R/(W)* Timer counter TCNT R/W Reset control/status register RSTCSR R/(W)* 3 3 Initial Value Write*2 Read H'18 H'FFBC H'FFBC H'00 H'FFBC H'FFBD H'1F H'FFBE H'FFBF Notes: 1. Lower 16 bits of the address. 2.
PAGE 486
13.2 Register Descriptions 13.2.1 Timer Counter (TCNT) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TCNT is an 8-bit readable/writable*1 up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR.
PAGE 487
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal*1 when TCNT overflows.
PAGE 488
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access.
PAGE 489
13.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 13-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address.
PAGE 490
13.3 Operation 13.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal*1 is output. This is shown in figure 13-4.
PAGE 491
13.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 13-5. This function can be used to generate interrupt requests at regular intervals.
PAGE 492
13.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2357 Group chip. Figure 13-7 shows the timing in this case. Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392, or H8S/2390.
PAGE 493
13.5 Usage Notes 13.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13-8 shows this operation. TCNT write cycle T1 T2 ø Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13-8 Contention between TCNT Write and Increment 13.5.
PAGE 494
H8S/2357 Group Reset input Reset signal to entire system RES WDTOVF* Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or H8S/2390. Figure 13-9 Circuit for System Reset by WDTOVF Signal (Example) 13.5.5 Internal Reset in Watchdog Timer Mode The H8S/2357 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset.
PAGE 495
Section 14 Serial Communication Interface (SCI) 14.1 Overview The H8S/2357 Group is equipped with a three-channel serial communication interface (SCI). All three channels have the same functions. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 14.1.1 Features SCI features are listed below.
PAGE 496
• Four interrupt sources  Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive error — that can issue requests independently  The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer • Module stop mode can be set  As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode.
PAGE 497
14.1.2 Block Diagram Bus interface Figure 14-1 shows a block diagram of the SCI.
PAGE 498
14.1.4 Register Configuration The SCI has the internal registers shown in table 14-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format, and the bit rate, and to control transmitter/receiver.
PAGE 499
14.2 Register Descriptions 14.2.1 Receive Shift Register (RSR) Bit : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 14.2.
PAGE 500
14.2.4 Transmit Data Register (TDR) Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR.
PAGE 501
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
PAGE 502
For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication Function. Bit 2 MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0.
PAGE 503
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1.
PAGE 504
The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.
PAGE 505
For details of clock source selection, see table 14-9 in section 14.3, Operation.
PAGE 506
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
PAGE 507
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER Description 0 [Clearing condition] (Initial value)*1 When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* 2 Notes: 1.
PAGE 508
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. 14.2.
PAGE 509
ø = 3.6864 MHz ø = 4 MHz ø = 4.9152 MHz ø = 5 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.
PAGE 510
ø = 9.8304 MHz Bit Rate (bit/s) n N Error (%) 110 2 174 150 2 300 ø = 10 MHz N Error (%) –0.26 2 177 127 0.00 2 1 255 0.00 600 1 127 1200 0 2400 ø = 12 MHz ø = 12.288 MHz N Error (%) n N Error (%) –0.25 2 212 0.03 2 217 0.08 129 0.16 2 155 0.16 2 159 0.00 2 64 0.16 2 77 0.16 2 79 0.00 0.00 1 129 0.16 1 155 0.16 1 159 0.00 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.
PAGE 511
ø = 18 MHz ø = 19.6608 MHz Bit Rate (bit/s) n N Error (%) 110 3 79 150 2 300 ø = 20 MHz N Error (%) n N Error (%) –0.12 3 86 0.31 3 88 –0.25 233 0.16 2 255 0.00 3 64 0.16 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 –0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.
PAGE 512
The BRR setting is found from the following formulas. Asynchronous mode: N= ø 64 × 2 2n–1 ×B × 10 6 – 1 Clocked synchronous mode: N= Where B: N: ø: n: ø 8×2 2n–1 ×B × 10 6 – 1 Bit rate (bit/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.
PAGE 513
Table 14-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 14-6 and 14-7 show the maximum bit rates with external clock input. Table 14-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.
PAGE 514
Table 14-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.
PAGE 515
14.2.9 Smart Card Mode Register (SCMR) Bit : 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 R/W — — — — R/W R/W — R/W : SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSBfirst or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see section 15.2.
PAGE 516
14.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP7 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode.
PAGE 517
14.3 Operation 14.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 14-8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 14-9.
PAGE 518
Table 14-8 SMR Settings and Serial Transfer Format Selection SMR Settings SCI Transfer Format Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 C/A CHR MP PE STOP Mode Data Length Multi Processor Bit 0 0 0 0 0 Asynchronous 8-bit data No 1 mode 1 Parity Bit Stop Bit Length No 1 bit 2 bits 0 Yes 1 1 0 2 bits 0 7-bit data No 1 1 1 0 — 1 1 — — 1 bit 2 bits Yes 1 0 1 bit 1 bit 2 bits 0 Asynchronous — 1 — 0 mode (multiprocessor format) — 1 — — 8-bit data Yes No 1 bit 2
PAGE 519
14.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication.
PAGE 520
Table 14-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length CHR PE MP STOP 1 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 — 1 0 S 8-bit data MPB STOP 0 — 1 1 S 8-bit data MPB STOP STOP 1 —
PAGE 521
Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14-9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
PAGE 522
Figure 14-4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR.
PAGE 523
• Serial data transmission (asynchronous mode) Figure 14-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization [1] Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
PAGE 524
[b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit.
PAGE 525
• Serial data reception (asynchronous mode) Figure 14-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
PAGE 526
[3] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER= 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 14-7 Sample Serial Reception Data Flowchart (cont) Rev.6.00 Oct.28.
PAGE 527
In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR.
PAGE 528
Table 14-11 Receive Errors and Conditions for Occurrence Receive Error Abbreviation Occurrence Condition Data Transfer Overrun error ORER When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR. Framing error FER When the stop bit is 0 Parity error PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR. in SMR Receive data is transferred from RSR to RDR.
PAGE 529
14.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
PAGE 530
Data Transfer Operations: • Multiprocessor serial data transmission Figure 14-10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission.
PAGE 531
In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output.
PAGE 532
• Multiprocessor serial data reception Figure 14-12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1.
PAGE 533
[5] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 14-12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev.6.00 Oct.28.
PAGE 534
Figure 14-13 shows an example of SCI operation for multiprocessor format reception.
PAGE 535
14.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer.
PAGE 536
Data Transfer Operations: • SCI initialization (clocked synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized.
PAGE 537
• Serial data transmission (clocked synchronous mode) Figure 14-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] Initialization Start transmission Read TDRE flag in SSR [2] No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin.
PAGE 538
In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses.
PAGE 539
• Serial data reception (clocked synchronous mode) Figure 14-18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible.
PAGE 540
In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR.
PAGE 541
• Simultaneous serial data transmission and reception (clocked synchronous mode) Figure 14-20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations.
PAGE 542
14.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receivedata-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 14-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently.
PAGE 543
Table 14-12 SCI Interrupt Sources Channel Interrupt Source Description DTC Activation DMAC Activation 0 ERI Interrupt due to receive error (ORER, FER, or PER) Not possible Not possible RXI Interrupt due to receive data full state (RDRF) Possible Possible TXI Interrupt due to transmit data empty state (TDRE) Possible Possible TEI Interrupt due to transmission end (TEND) Not possible Not possible ERI Interrupt due to receive error (ORER, FER, or PER) Not possible Not possible RXI Int
PAGE 544
14.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag.
PAGE 545
Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
PAGE 546
Where M N D L F : Reception margin (%) : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 – 1 2 × 16 ) × 100% = 46.875% ... Formula (2) However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
PAGE 547
Section 15 Smart Card Interface 15.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.1.1 Features Features of the Smart Card interface supported by the H8S/2357 Group are as follows.
PAGE 548
15.1.2 Block Diagram Bus interface Figure 15-1 shows a block diagram of the Smart Card interface.
PAGE 549
15.1.4 Register Configuration Table 15-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface (SCI).
PAGE 550
15.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 15.2.1 Smart Card Mode Register (SCMR) Bit : 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 R/W — — — — R/W R/W — R/W : SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode.
PAGE 551
15.2.2 Serial Status Register (SSR) Bit : 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Initial value : R/W : Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5—Operate in the same way as for the normal SCI.
PAGE 552
15.2.3 Serial Mode Register (SMR) Bit : 7 6 5 4 3 2 1 0 GM CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Set value* : GM 0 1 O/E 1 0 CKS1 CKS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Note: * When the Smart Card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2. The function of bit 7 of SMR changes in Smart Card interface mode. Bit 7—GSM Mode (GM): Sets the Smart Card interface function to GSM mode.
PAGE 553
15.2.4 Serial Control Register (SCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W In Smart Card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 14.2.6, Serial Control Register (SCR).
PAGE 554
15.3 Operation 15.3.1 Overview The main functions of the Smart Card interface are as follows. • • • • • One frame consists of 8-bit data plus a parity bit. In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit.
PAGE 555
15.3.3 Data Format Figure 15-3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted.
PAGE 556
15.3.4 Register Settings Table 15-3 shows a bit map of the registers used by the Smart Card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below.
PAGE 557
• Direct convention (SDIR = SINV = O/E = 0) (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card.
PAGE 558
Table 15-5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0) ø (MHz) N 10.00 10.714 13.00 14.285 16.00 18.00 20.00 0 13441 14400 17473 19200 21505 24194 26882 1 6720 7200 8737 9600 10753 12097 13441 2 4480 4800 5824 6400 7168 8065 8961 Note: Bit rates are rounded to the nearest whole number. The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below.
PAGE 559
15.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR.
PAGE 560
Start Initialization Start transmission ERS=0? No Yes Error processing No TEND=1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS=0? Yes Error processing No TEND=1? Yes Clear TE bit to 0 End Figure 15-4 Example of Transmission Processing Flow Rev.6.00 Oct.28.
PAGE 561
TDR (1) Data write Data 1 (2) Transfer from TDR to TSR Data 1 (3) Serial data output Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to
PAGE 562
Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 15-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0.
PAGE 563
If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed.
PAGE 564
and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC or DTC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically even in retransmission following an error.
PAGE 565
Software standby Normal operation [1] [2] [3] [4] [5] [6] Normal operation [7] [8] [9] Figure 15-9 Clock Halt and Restart Procedure Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to Smart Card mode operation.
PAGE 566
M = (0.5 – 1 ) – (L – 0.5) F –  D – 0.5 2N (1 + F) × 100% N Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 – 1/2 × 372) × 100% = 49.
PAGE 567
[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated.
PAGE 568
Rev.6.00 Oct.28.
PAGE 569
Section 16 A/D Converter 16.1 Overview The H8S/2357 Group incorporates a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. 16.1.1 Features A/D converter features are listed below • 10-bit resolution • Eight input channels • Settable analog conversion voltage range  Conversion of analog voltages with the reference voltage pin (Vref ) as the analog reference voltage • High-speed conversion  Minimum conversion time: 6.
PAGE 570
16.1.2 Block Diagram Figure 16-1 shows a block diagram of the A/D converter.
PAGE 571
Table 16-1 A/D Converter Pins Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and A/D conversion reference voltage Reference voltage pin Vref Input A/D conversion reference voltage Analog input pin 0 AN0 Input Group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog in
PAGE 572
16.2 Register Descriptions 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
PAGE 573
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
PAGE 574
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Group Selection Channel Selection CH2 CH1 CH0 Single Mode (SCAN=0) Scan Mode (SCAN=1) 0 0 0 AN0 (Initial value) AN0 1 AN1 AN0, AN1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 1 1 0 1 16.2.
PAGE 575
16.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode.
PAGE 576
16.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP.
PAGE 577
On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again.
PAGE 578
16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0.
PAGE 579
16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a on-chip sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D conversion timing. Table 16-4 indicates the A/D conversion time. As indicated in figure 16-5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR.
PAGE 580
16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 16-6 shows the timing.
PAGE 581
16.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. (2) Relation between AV CC, AVSS and V CC, VSS As the relationship between AVCC, AVSS and V CC, VSS, set AVSS = VSS . If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open.
PAGE 582
AVCC Vref 100 Ω Rin* 2 *1 AN0 to AN7 *1 0.1 µF Notes: AVSS Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 16-7 Example of Analog Input Protection Circuit A/D Conversion Precision Definitions: H8S/2357 Group A/D conversion precision definitions are given below.
PAGE 583
Digital output Ideal A/D conversion characteristic 111 110 101 100 011 Quantization error 010 001 000 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 16-8 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 16-9 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2357 Group analog input is de
PAGE 584
However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kohm, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted.
PAGE 585
Section 17 D/A Converter 17.1 Overview The H8S/2357 Group includes a two-channel D/A converter. 17.1.1 Features D/A converter features are listed below • • • • • • 8-bit resolution Two output channels Maximum conversion time of 10 µs (with 20 pF load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Module stop mode can be set  As the initial setting, D/A converter operation is halted. Register access is enabled by exiting module stop mode. 17.1.
PAGE 586
17.1.3 Pin Configuration Table 17-1 summarizes the input and output pins of the D/A converter. Table 17-1 Pin Configuration 17.1.
PAGE 587
17.2 Register Descriptions 17.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) Bit : 7 Initial value : R/W : 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 17.2.
PAGE 588
Bit 5—D/A Enable (DAE): The DAOE0 and DAOE1 bits both control D/A conversion. When the DAE bit is cleared to 0, the channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, the channel 0 and 1 D/A conversions are controlled together. Output of resultant conversions is always controlled independently by the DAOE0 and DAOE1 bits.
PAGE 589
17.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 17-2 shows the timing of this operation.
PAGE 590
Rev.6.00 Oct.28.
PAGE 591
Section 18 RAM 18.1 Overview The H8S/2357, H8S/2352, H8S/2398, and H8S/2392 have 8 kbytes of on-chip high-speed static RAM. The H8S/2394 has 32 kbytes of on-chip high-speed static RAM. The H8S/2390 has 4 kbytes of on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 16-bit bus, and accessing both byte data and word data can be performed in a single state. Thus, high-speed transfer of word data is possible.
PAGE 592
18.2 Register Descriptions 18.2.1 System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG — — RAME 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W — R/W R/W The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released.
PAGE 593
Section 19 ROM 19.1 Overview This series has 256, or 128 kbytes of flash memory, 256 or 128 kbytes of masked ROM, or 128 kbytes of PROM. The ROM is connected to the H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL.
PAGE 594
19.2 Register Descriptions 19.2.1 Mode Control Register (MDCR) Bit : 7 6 5 4 3 2 1 0 — — — — — MDS2 MDS1 MDS0 Initial value : 1 0 0 0 0 —* —* —* R/W — — — — — R R R : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2357 Group. Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 0.
PAGE 595
19.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD 2, MD1, and MD0) and bit EAE in BCRL. These settings are shown in tables 19-2 and 19-3.
PAGE 596
Table 19-3 Operating Modes and ROM Area (ZTAT or Masked ROM, ROMless, Versions H8S/2398F-ZTAT) Mode Pin BCRL Operating Mode MD2 MD1 MD0 EAE On-Chip ROM Mode 0 0 0 0 — — — Disabled 0 Enabled (128 kbytes)* 1 1 Enabled (64 kbytes) 0 Enabled (128 kbytes)* 1 1 Enabled (64 kbytes) — Mode 1 1 Mode 2* 2 Mode 3* 2 Mode 4* 3 1 1 Advanced expanded mode with on-chip ROM disabled 1 0 Mode 5* 3 Advanced expanded mode with on-chip ROM disabled Mode 6 Mode 7 0 Advanced expanded mode
PAGE 597
19.4.2 Socket Adapter and Memory Map Programs can be written and verified by attaching a socket adapter to the PROM programmer to convert from a 120/128pin arrangement to a 32-pin arrangement. Table 19-5 gives ordering information for the socket adapter, and figure 19-2 shows the wiring of the socket adapter. Figure 19-3 shows the memory map in PROM mode.
PAGE 598
Table 19-5 Socket Adapter Microcontroller Package Socket Adapter H8S/2357 120 pin TQFP (TFP-120) HS2655ESNS1H 128 pin QFP (FP-128B) HS2655ESHS1H Addresses in MCU mode Addresses in PROM mode H'000000 H'00000 On-chip PROM H'01FFFF H'1FFFF Figure 19-3 Memory Map in PROM Mode Rev.6.00 Oct.28.
PAGE 599
19.5 Programming (H8S/2357 ZTAT) 19.5.1 Overview Table 19-6 shows how to select the program, verify, and program-inhibit modes in PROM mode.
PAGE 600
19.5.2 Programming and Verification An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. It leaves the data H'FF in unused addresses. Figure 19-4 shows the basic high-speed programming flowchart. Tables 19-7 and 19-8 list the electrical characteristics of the chip during programming. Figure 19-5 shows a timing chart.
PAGE 601
Table 19-7 DC Characteristics in PROM Mode Conditions: VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, VSS = 0 V, Ta = 25°C ± 5°C Item Symbol Min Typ Max Test Unit Conditions — VCC + 0.3 V Input high voltage EO7 to EO 0, EA16 to EA 0, OE, CE, PGM VIH 2.4 Input low voltage EO7 to EO 0, EA16 to EA0, OE, CE, PGM VIL –0.3 — 0.8 V Output high voltage EO7 to EO 0 VOH 2.4 — — V I OH = –200 µA Output low voltage EO7 to EO 0 VOL — — 0.45 V I OL = 1.
PAGE 602
Program Verify Address tAS tAH Input data Data tDS VPP VCC Output data tDH tDF VPP VCC tVPS VCC+1 VCC tVCS CE tCES PGM tPW tOES tOE tOPW* OE Note: * tOPW is defined by the value shown in the flowchart. Figure 19-5 PROM Programming/Verification Timing 19.5.3 Programming Precautions • Program using the specified voltages and timing. The programming voltage (VPP) in PROM mode is 12.5 V. If the PROM programmer is set to Renesas Technology HN27C101 specifications, VPP will be 12.5 V.
PAGE 603
19.5.4 Reliability of Programmed Data An effective way to assure the data retention characteristics of the programmed chips is to bake them at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 19-6 shows the recommended screening procedure.
PAGE 604
19.6 Overview of Flash Memory (H8S/2357 F-ZTAT) 19.6.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units). When erasing multiple blocks, the individual blocks must be erased sequentially.
PAGE 605
Block Diagram Internal address bus Internal data bus (16 bits) SYSCR2 FLMCR1 Module bus 19.6.2 Bus interface/controller FLMCR2 Operating mode FWE pin Mode pins EBR1 EBR2 RAMER Flash memory (128 kbytes) Legend: SYSCR2: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: System control register 2 Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Figure 19-7 Block Diagram of Flash Memory Rev.6.00 Oct.28.
PAGE 606
19.6.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 19-8. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode.
PAGE 607
On-Board Programming Modes • Boot mode 2. Programming control program transfer When boot mode is entered, the boot program in the H8S/2357 chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. "# , ! ! 1. Initial state The old program version or data remains written in the flash memory.
PAGE 608
• User program mode 2. Programming/erase control program transfer When the FWE pin is driven high, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. , , ! 1.
PAGE 609
Flash Memory Emulation in RAM • Reading Overlap Data in User Mode and User Program Mode Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read.
PAGE 610
Differences between Boot Mode and User Program Mode Table 19-9 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Program/program-verify Erase/erase-verify Note: * To be provided by the user, in accordance with the recommended algorithm.
PAGE 611
19.6.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 19-10. Table 19-10 Flash Memory Pins 19.6.
PAGE 612
19.7 Register Descriptions 19.7.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value —* 0 0 0 0 0 0 0 Read/Write R R/W — — R/W R/W R/W R/W Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1.
PAGE 613
Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.
PAGE 614
19.7.2 Flash Memory Control Register 2 (FLMCR2) Bit 7 6 5 4 3 2 1 0 FLER — — — — — ESU PSU Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — R/W R/W FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode.
PAGE 615
Bit 0 PSU Description 0 Program setup cleared 1 Program setup (Initial value) [Setting condition] When FWE = 1, and SWE = 1 19.7.
PAGE 616
19.7.4 System Control Register 2 (SYSCR2) Bit 7 6 5 4 3 2 1 0 — — — — FLSHE — — — Initial value 0 0 0 0 0 0 0 0 Read/Write — — — — R/W — — — SYSCR2 is an 8-bit readable/writable register that controls on-chip flash memory (in F-ZTAT versions). SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 is available only in the F-ZTAT version.
PAGE 617
Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected.
PAGE 618
19.8 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19-14. For a diagram of the transitions to the various flash memory modes, see figure 19-8.
PAGE 619
Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate MCU measures low period of H'00 data transmitted by host MCU calculates bit rate and sets value in bit rate register After bit rate adjustment, MCU transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, MCU transmits one H'AA data byte to host Host tra
PAGE 620
Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) Stop bit High period (1 or more bits) Figure 19-16 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the H8S/2357 MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity.
PAGE 621
H'FFDC00 H'FFE3FF Boot program area*1 (2 kbytes) Programming control program area (6 kbytes) H'FFFB7F H'FFFBFF (128 bytes)*2 Notes: 1. The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. 2. The area from H'FFFB80 to H'FFFBFF (128 bytes) is used by the boot program.
PAGE 622
• If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1.
PAGE 623
Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin.
PAGE 624
19.9 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased.
PAGE 625
19-19) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least (η) µs, then clear the SWE bit in FLMCR1 to 0. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Start Perform programming in the erased state.
PAGE 626
19.9.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19-20. The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of programming operations (N) are shown in table 22.42 in section 22.7.6, Flash Memory Characteristics.
PAGE 627
Start *1 Set SWE bit in FLMCR1 Wait (x) µs *2 n=1 Set EBR1, EBR2 *4 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs *2 Start of erase Set E bit in FLMCR1 Wait (z) ms *2 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) µs *2 Clear ESU bit in FLMCR2 Wait (β) µs *2 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *2 Set block start address to verify address H'FF dummy write to verify address Increment address Wait (ε) µs *2 Read verify data *3 Verify data = all 1? NG OK NG Last address of
PAGE 628
19.10 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.10.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 19-16.
PAGE 629
19.10.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in RAMER. When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 19-17.
PAGE 630
Normal Operating mode Program mode Erase mode Reset or hardware standby (hardware protection) RES = 0 or STBY = 0 RD VF PR ER FLER = 0 Error occurrence (software standby) RD VF PR ER FLER = 0 RES = 0 or STBY = 0 Error occurrence RES = 0 or STBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 in
PAGE 631
19.11 Flash Memory Emulation in RAM 19.11.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode.
PAGE 632
19.11.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. H'000000 EB0 H'000400 EB1 H'000800 EB2 H'000C00 This area can be accessed from both the RAM area and flash memory area EB3 Flash memory EB4 to EB9 H'FFDC00 H'FFDFFF On-chip RAM Figure 19.23 Example of RAM Overlap Operation Example in Which Flash Memory Block Area (EB1) is Overlapped 1.
PAGE 633
19.12 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* 1, to give priority to the program or erase operation. There are three reasons for this: 1.
PAGE 634
19.13 Flash Memory Programmer Mode 19.13.1 Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device types with 128-kbyte on-chip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
PAGE 635
19.13.3 Programmer Mode Operation Table 19-19 shows how the different operating modes are set when using programmer mode, and table 19-20 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. • Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of autoprogramming. • Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory.
PAGE 636
Table 19-20 Programmer Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write × H'00 Read RA Dout Auto-program mode 129 Write × H'40 Write PA Din Auto-erase mode 2 Write × H'20 Write × H'20 Status read mode 2 Write × H'71 Write × H'71 Legend: RA: Read address PA: Program address ×: Don’t care Notes: 1. In auto-program mode.
PAGE 637
Command write Memory read mode Address Address stable CE OE WE twep tceh tnxtc tces tf tr Data Data H'00 tdh tds Note: Data is latched on the rising edge of WE. Figure 19-25 Memory Read Mode Timing Waveforms after Command Write Table 19-22 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 5.
PAGE 638
×× mode command write Address Address stable twep CE tceh tnxtc OE tces WE tf Data Data tr H'×× tdh tds Note: Do not enable WE and OE at the same time. Figure 19-26 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 19-23 AC Characteristics in Memory Read Mode Conditions: VCC = 5.
PAGE 639
Address Address stable Address stable tacc CE tce tce OE toe toe WE tdf tdf tacc Data VIH Data Data toh toh Figure 19-28 Timing Waveforms for CE/OE Clocked Read 19.13.5 Auto-Program Mode AC Characteristics Table 19-24 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.
PAGE 640
FWE tpns tpnh Address stable Address tceh tas CE tah tnxtc OE tnxtc twep WE Data transfer 1 byte to 128 bytes tces twsts tspa twrite (1 to 3000 ms) Programming operation end identification signal tr tf I/O7 tds tdh Programming normal end identification signal I/O6 Programming wait Data H'40 Data Data I/O0 to I/O5 = 0 Figure 19-29 Auto-Program Mode Timing Waveforms Notes on Use of Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously.
PAGE 641
19.13.6 Auto-Erase Mode AC Characteristics Table 19-25 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.
PAGE 642
• The status polling I/O6 and I/O7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. 19.13.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed.
PAGE 643
Table 19-27 Status Read Mode Return Commands Pin Name I/O 7 Attribute I/O 6 Normal Command end error identification Initial value 0 0 Indications Normal end: 0 Command error: 1 Abnormal end: 1 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 Programming error Erase error — — ProgramEffective ming or address error erase count exceeded 0 0 0 0 0 — Count Effective exceeded: 1 address Otherwise: 0 error: 1 ProgramErase — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 I/O 0 0 Otherwise: 0
PAGE 644
VCC tosc1 tbmv RES tdwn Memory read Auto-program mode mode Auto-erase mode Command wait state FWE Command Don't care wait state Normal/ abnormal end identification Don't care Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 19-32 Oscillation Stabilization Time, Programmer Mode Setup Time, and Power Supply Fall Sequence 19.13.
PAGE 645
• In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during program execution in flash memory. • Do not apply FWE if program runaway has occurred. • Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 and FLMCR2 are cleared. • Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE.
PAGE 646
Wait time: x Programming and erase possible φ min 0 µs t OSC1 VCC t MDS* 3 FWE min 0 µs MD2 to MD0 * 1 t MDS* 3 RES SWE set SWE clear SWE bit Flash memory access disabled period (x: Wait time after SWE setting) * 2 Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1. Always fix the level by pulling down or pulling up the mode pins (MD2 to MD0) until powering off, except for mode switching. 2. See section 22.7.
PAGE 647
Wait time: x Programming and erase possible φ min 0 µs t OSC1 VCC FWE MD 2 to MD 0 * 1 t MDS* 3 RES SWE set SWE clear SWE bit Flash memory access disabled period (x: Wait time after SWE setting) * 2 Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1. Always fix the level by pulling down or pulling up the mode pins (MD2 to MD0) up to powering off, except for mode switching. 2. See section 22.7.
PAGE 648
Programming and Wait erase Wait time: x possible time: x Programming and Wait time: x erase possible Programming and erase possible Wait time: x Programming and erase possible φ t OSC1 VCC min 0µs FWE *2 t MDS t MDS MD 2 to MD 0 t MDS tRESW RES SWE set SWE clear SWE bit Mode switching * 1 Boot mode Mode User switching * 1 mode User program mode User mode Flash memory access disabled period (x: Wait time after SWE setting) * 3 Flash memory reprogammable period (Flash memory program execution a
PAGE 649
19.15 Overview of Flash Memory (H8S/2398 F-ZTAT) 19.15.1 Features The H8S/2398 F-ZTAT have 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
PAGE 650
19.15.2 Overview Block Diagram Internal address bus Module bus Internal data bus (16 bits) FLMCR1 FLMCR2 Bus interface/controller EBR1 Operating mode EBR2 RAMER SYSCR2 Flash memory (256 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: SYSCR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2 Figure 19-36 Block Diagram of Flash Memory Rev.6.00 Oct.28.
PAGE 651
19.15.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 19-37. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode.
PAGE 652
19.15.4 On-Board Programming Modes • Boot mode 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. "#, ! 1. Initial state The old program version or data remains written in the flash memory.
PAGE 653
• User program mode 2. Programming/erase control program transfer Executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. , , ! 1. Initial state (1) The program that will transfer the programming/erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory.
PAGE 654
19.15.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read.
PAGE 655
19.15.6 Differences between Boot Mode and User Program Mode Table 19-30 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm. 19.15.
PAGE 656
19.15.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 19-31. Table 19-31 Flash Memory Pins 19.15.
PAGE 657
19.16 Register Descriptions 19.16.1 Flash Memory Control Register 1 (FLMCR1) Bit : 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P Initial value : 1 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/W R/W : FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1, then setting the EV or PV bit.
PAGE 658
Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.
PAGE 659
19.16.2 Flash Memory Control Register 2 (FLMCR2) Bit : 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value : 0 0 0 0 0 0 0 0 R/W R — — — — — — — : FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
PAGE 660
19.16.4 Bit Erase Block Registers 2 (EBR2) : 7 6 5 4 3 2 1 0 EBR2 — — — — EB11 EB10 EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 R/W — — — — R/W R/W R/W R/W : EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected.
PAGE 661
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
PAGE 662
Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 19-34.
PAGE 663
19.17.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2398 F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI.
PAGE 664
Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host
PAGE 665
Automatic SCI Bit Rate Adjustment: When boot mode is initiated, H8S/2398 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
PAGE 666
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19-46. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required.
PAGE 667
Do not change the mode pin input levels in boot mode. • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode*2. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer.
PAGE 668
19.18 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased.
PAGE 669
program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Start of programming Write pulse application subroutine Sub-routine write pulse Start Enable WDT Set SWE bit in FLMCR1 Wait (x) µs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU bit in FLMCR1 Wait (y) µs *6 Perform programming in the erased state.
PAGE 670
19.18.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19-49. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.3.6, Flash Memory Characteristics.
PAGE 671
Start *1 Set SWE bit in FLMCR1 Wait (x) µs *2 n=1 Set EBR1, EBR2 *4 Enable WDT Set ESU bit in FLMCR1 Wait (y) µs *2 Start of erase Set E bit in FLMCR1 Wait (z) ms *2 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) µs *2 Clear ESU bit in FLMCR1 Wait (β) µs *2 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *2 Set block start address to verify address H'FF dummy write to verify address Increment address Wait (ε) µs *2 Read verify data *3 Verify data = all 1? NG OK NG Last address of
PAGE 672
19.19 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.19.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset. (See table 19-37.
PAGE 673
19.19.2 Software Protection Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. (See table 19-38.
PAGE 674
19.19.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered.
PAGE 675
19.20 Flash Memory Emulation in RAM 19.20.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode.
PAGE 676
19.20.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFDC00 H'FFEBFF Flash memory EB8 to EB11 On-chip RAM H'FFFBFF H'3FFFF Figure 19-52 Example of RAM Overlap Operation Example in Which Flash Memory Block Area EB1 is Overlapped 1.
PAGE 677
19.21 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* 1, to give priority to the program or erase operation. There are three reasons for this: 1.
PAGE 678
19.22.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is connected to the chip as shown in figure 19-54. Figure 19-53 shows the on-chip ROM memory map and figure 19-54 show the socket adapter pin assignments. MCU mode address H8S/2398 F-ZTAT Programmer mode address H'00000 H'00000000 On-chip ROM space (256 kbytes) H'0003FFFF H'3FFFF Figure 19-53 Memory Map in Programmer Mode Rev.6.00 Oct.28.
PAGE 679
H8S/2398 F-ZTAT Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) TFP-120 FP-128B Pin Name Pin No.
PAGE 680
19.22.3 Programmer Mode Operation Table 19-40 shows how the different operating modes are set when using programmer mode, and table 19-41 lists the commands used in programmer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory.
PAGE 681
19.22.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. • Command writes can be performed in memory read mode, just as in the command wait state. • Once memory read mode has been entered, consecutive reads can be performed. • After power-on, memory read mode is entered.
PAGE 682
Table 19-43 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 5.
PAGE 683
A18 to A0 Address stable CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7 to I/O0 Figure 19-57 Timing Waveforms for CE/OE Enable State Read Address stable A18 to A0 Address stable tce tce CE toe toe OE WE VIH tacc tacc toh toh tdf tdf I/O7 to I/O0 Figure 19-58 Timing Waveforms for CE/OE Clocked Read 19.22.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed.
PAGE 684
AC Characteristics Table 19-45 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.
PAGE 685
19.22.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation). • Status polling I/O6 and I/O7 pin information is retained until the next command write.
PAGE 686
19.22.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 19-47 AC Characteristics in Status Read Mode Conditions: VCC = 5.
PAGE 687
Table 19-48 Status Read Mode Return Commands Pin Name I/O 7 Attribute I/O 6 Normal Command end error identification Initial value 0 0 Indications Normal end: 0 Command error: 1 Abnormal end: 1 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 Programming error Erase error — — ProgramEffective ming or address error erase count exceeded 0 0 0 0 0 — Count Effective exceeded: 1 address Otherwise: 0 error: 1 ProgramErase — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 I/O 0 0 Otherwise: 0
PAGE 688
19.22.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out auto-erasing before autoprogramming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology.
PAGE 689
one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Rev.6.
PAGE 690
Rev.6.00 Oct.28.
PAGE 691
Section 20 Clock Pulse Generator 20.1 Overview The H8S/2357 Group has a on-chip clock pulse generator (CPG) that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-speed clock divider, and a bus master clock selection circuit. 20.1.1 Block Diagram Figure 20-1 shows a block diagram of the clock pulse generator.
PAGE 692
20.2 Register Descriptions 20.2.1 System Clock Control Register (SCKCR) Bit : 7 6 5 4 3 2 1 0 PSTOP — — — — SCK2 SCK1 SCK0 Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W —/(R/W)* — — R/W R/W R/W SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
PAGE 693
20.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 20.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20-2. Select the damping resistance R d according to table 20-2. An AT-cut parallel-resonance crystal should be used.
PAGE 694
Note on Board Design: When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 20-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B H8S/2357 Group CL2 XTAL EXTAL CL1 Figure 20-4 Example of Incorrect Board Design 20.3.
PAGE 695
Table 20-4 and figure 20-6 show the input conditions for the external clock. Table 20-4 External Clock Input Conditions VCC = 2.7 V to 5.5 V VCC = 5.
PAGE 696
Rev.6.00 Oct.28.
PAGE 697
Section 21 Power-Down Modes 21.1 Overview In addition to the normal program execution state, the H8S/2357 Group has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
PAGE 698
21.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 21-2 summarizes these registers. Table 21-2 Power-Down Mode Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'08 H'FF38 System clock control register SCKCR R/W H'00 H'FF3A Module stop control register H MSTPCRH R/W H'3F H'FF3C Module stop control register L MSTPCRL R/W H'FF H'FF3D Note: * Lower 16 bits of the address. Rev.6.
PAGE 699
21.2 Register Descriptions 21.2.1 Standby Control Register (SBYCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — — 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W — — R/W SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode.
PAGE 700
Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS) is retained or set to the high-impedance state in software standby mode. Bit 3 OPE Description 0 In software standby mode, address bus and bus control signals are high-impedance 1 In software standby mode, address bus and bus control signals retain output state (Initial value) Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0.
PAGE 701
Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 Bit 1 SCK1 Bit 0 SCK0 Description 0 0 0 Bus master in high-speed mode 1 Medium-speed clock is ø/2 0 Medium-speed clock is ø/4 1 Medium-speed clock is ø/8 0 Medium-speed clock is ø/16 1 Medium-speed clock is ø/32 — — 1 1 0 1 21.2.
PAGE 702
21.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DMAC and DTC) also operate in mediumspeed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (ø).
PAGE 703
21.5 Module Stop Mode 21.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21-3 shows MSTP bits and the corresponding on-chip supporting modules.
PAGE 704
21.5.2 Usage Notes DMAC/DTC Module Stop: Depending on the operating status of the DMAC or DTC, the MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 7, DMA Controller, and section 8, Data Transfer Controller. On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode.
PAGE 705
21.6 Software Standby Mode 21.6.1 Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained.
PAGE 706
Table 21-4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21-4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz Unit 0 0 1 1 0 1 0 8,192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 1 16,384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 0 32,768 states 1.6 2.0 2.7 3.3 4.1 5.5 1 65,536 states 3.3 4.1 5.5 6.6 0 131,072 states 6.6 1 262,144 states 13.1 16.4 21.
PAGE 707
Oscillator ø NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 21-2 Software Standby Mode Application Example 21.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained.
PAGE 708
21.7 Hardware Standby Mode 21.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state.
PAGE 709
21.8 ø Clock Output Disabling Function Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle, and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set. Table 21-5 shows the state of the ø pin in each processing state.
PAGE 710
Rev.6.00 Oct.28.
PAGE 711
Section 22 Electrical Characteristics 22.1 Electrical Characteristics of Masked ROM Version (H8S/2398) and ROMless Versions (H8S/2394, H8S/2392, and H8S/2390) 22.1.1 Absolute Maximum Ratings Table 22-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC* –0.3 to +7.0 V Input voltage (except port 4) Vin –0.3 to + VCC +0.3 V Input voltage (port 4) Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.3 V Analog power supply voltage AVCC –0.3 to +7.
PAGE 712
22.1.2 DC Characteristics Table 22-2 lists the DC characteristics. Table 22-3 lists the permissible output currents. Table 22-2 DC Characteristics Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20 to +75°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Port 2, P64 to P6 7, PA4 to PA 7 Symbol Min Typ Max Unit VT– 1.0 — — V — — VCC × 0.7 V VT – VT 0.4 — — V VIH VCC – 0.
PAGE 713
Item Current dissipation* 2 Analog power supply current Symbol Min Typ — Sleep mode — Standby mode* 3 — 0.8 2.0 (5.0 V) mA — 0.01 5.0 µA — 2.2 3.0 (5.0 V) mA — 0.01 5.0 µA 2.0 — — V Normal operation During A/D and D/A conversion I CC * 4 Al CC Idle Reference current During A/D and D/A conversion Al CC Idle RAM standby voltage VRAM Max Unit Test Conditions 46 69 (5.0 V) mA f = 20 MHz 37 56 (5.0 V) mA f = 20 MHz — 0.
PAGE 714
The chip 2 kΩ Port Darlington Pair Figure 22-1 Darlington Pair Drive Circuit (Example) The chip 600 Ω Ports 1, A to C LED Figure 22-2 LED Drive Circuit (Example) 22.1.3 AC Characteristics Figure 22-3 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V Figure 22-3 Output Load Circuit Rev.6.00 Oct.28.
PAGE 715
(1) Clock Timing Table 22-4 lists the clock timing Table 22-4 Clock Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 716
EXTAL tDEXT tDEXT VCC STBY NMI tOSC1 tOSC1 RES ø Figure 22-5 Oscillator Settling Timing (2) Control Signal Timing Table 22-5 lists the control signal timing. Table 22-5 Control Signal Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 717
ø tRESS tRESS RES tRESW Figure 22-6 Reset Input Timing ø tNMIH tNMIS NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 22-7 Interrupt Input Timing Rev.6.00 Oct.28.
PAGE 718
(3) Bus Timing Table 22-6 lists the bus timing. Table 22-6 Bus Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø= 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item Test Symbol Min Max Unit Conditions Address delay time t AD — 20 ns Address setup time t AS 0.5 × t cyc – 15 — ns Figure 22-8 to Figure 22-15 Address hold time t AH 0.
PAGE 719
Condition Test Item Symbol Min Max Unit Conditions WR hold time t WCH 0.5 × t cyc – 10 — ns Figure 22-8 to Figure 22-15 CAS setup time t CSR 0.
PAGE 720
T1 T2 T3 ø tAD A23 to A0 tCSD1 tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 22-9 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.
PAGE 721
T1 T2 TW T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 22-10 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.
PAGE 722
Tp TC1 Tr TC2 ø tAD tAD A23 to A0 tAS tAH tPCH tCSD3 tACC4 CS5 to CS2 (RAS) tCSD2 tCASD tCASD tACC1 CAS tRDS tRDH tACC3 D15 to D0 (read) tWRD2 tWRD2 HWR, LWR (write) tWCS tWCH tWDH tWDD tWDS D15 to D0 (write) Figure 22-11 DRAM Bus Timing TRp TRr TRc1 TRc2 ø tCSD2 tCSD1 CS5 to CS2 (RAS) tCSR tCASD CAS Figure 22-12 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.
PAGE 723
TRp TRr TRc TRc ø tCSD2 tCSD2 CS5 to CS2 (RAS) tCASD tCASD CAS Figure 22-13 Self-Refresh Timing T1 T2 or T3 T1 T2 ø tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 22-14 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.
PAGE 724
T1 T2 or T3 T1 ø tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 22-15 Burst ROM Access Timing (One-State Access) ø tBRQS tBRQS BREQ tBACD tBACD BACK tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS Figure 22-16 External Bus Release Timing Rev.6.00 Oct.28.
PAGE 725
ø tBRQOD tBRQOD BREQO Figure 22-17 External Bus Request Output Timing (4) DMAC Timing Table 22-7 lists the DMAC timing. Table 22-7 DMAC Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 726
T1 T2 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK0 , DACK1 Figure 22-18 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.
PAGE 727
T1 T2 T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD2 tDACD1 DACK0, DACK1 Figure 22-19 DMAC Single Address Transfer Timing (Three-State Access) T1 T2 or T3 ø tTED tTED TEND0, TEND1 Figure 22-20 DMAC TEND Output Timing ø tDRQS tDRQH DREQ0, DREQ1 Figure 22-21 DMAC DREQ Intput Timing Rev.6.00 Oct.28.
PAGE 728
(5) Timing of On-Chip Supporting Modules Table 22-8 lists the timing of on-chip supporting modules. Table 22-8 Timing of On-Chip Supporting Modules Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 729
T1 T2 ø tPRS tPRH Ports 1 to 6, A to G (read) tPWD Ports 1 to 3, 5, 6, A to G (write) Figure 22-22 I/O Port Input/Output Timing ø tPOD PO15 to PO0 Figure 22-23 PPG Output Timing ø tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22-24 TPU Input/Output Timing Rev.6.00 Oct.28.
PAGE 730
ø tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 22-25 TPU Clock Input Timing ø tTMOD TMO0, TMO1 Figure 22-26 8-Bit Timer Output Timing ø tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 22-27 8-Bit Timer Clock Input Timing ø tTMRS TMRI0, TMRI1 Figure 22-28 8-Bit Timer Reset Input Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 22-29 SCK Clock Input Timing Rev.6.00 Oct.28.
PAGE 731
SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 22-30 SCI Input/Output Timing (Clock Synchronous Mode) ø tTRGS ADTRG Figure 22-31 A/D Converter External Trigger Input Timing 22.1.4 A/D Conversion Characteristics Table 22-9 lists the A/D conversion characteristics. Table 22-9 A/D Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 732
22.1.5 D/A Conversion Characteristics Table 22-10 lists the D/A conversion characteristics. Table 22-10 D/A Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) 22.2 Item Min Typ Max Unit Test Conditions Resolution 8 8 8 bits Conversion time — — 10 µs 20-pF capacitive load Absolute accuracy — ±1.0 ±1.
PAGE 733
22.3 Electrical Characteristics of H8S/2398 F-ZTAT 22.3.1 Absolute Maximum Ratings Table 22-11 Absolute Maximum Ratings Item Symbol 1 Value Unit –0.3 to +7.0 V Power supply voltage VCC* Input voltage (except port 4) Vin –0.3 to + VCC +0.3 V Input voltage (port 4) Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.3 V Analog power supply voltage AVCC –0.3 to +7.0 V Analog input voltage VAN –0.3 to AVCC +0.
PAGE 734
22.3.2 DC Characteristics Table 22-12 lists the DC characteristics. Table 22-13 lists the permissible output currents. Table 22-12 DC Characteristics Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20 to +75°C (regular specifications), T a = -40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Port 2, P64 to P6 7, PA4 to PA 7 Symbol Min Typ Max Unit VT– 1.0 — — V — — VCC × 0.7 V VT – VT 0.4 — — V VIH VCC – 0.
PAGE 735
Item Current dissipation* 2 Analog power supply current Symbol Min Typ — Sleep mode — Standby mode* 3 — 0.8 2.0 (5.0 V) mA — 0.01 5.0 µA — 2.2 3.0 (5.0 V) mA — 0.01 5.0 µA 2.0 — — V Normal operation During A/D and D/A conversion I CC * 4 Al CC Idle Reference current During A/D and D/A conversion Al CC Idle RAM standby voltage VRAM Max Unit Test Conditions 46 69 (5.0 V) mA f = 20 MHz 37 56 (5.0 V) mA f = 20 MHz — 0.
PAGE 736
The chip 2 kΩ Port Darlington Pair Figure 22-33 Darlington Pair Drive Circuit (Example) The chip 600 Ω Ports 1, A to C LED Figure 22-34 LED Drive Circuit (Example) 22.3.3 AC Characteristics Figure 22-35 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V Figure 22-35 Output Load Circuit Rev.6.00 Oct.28.
PAGE 737
(1) Clock Timing Table 22-14 lists the clock timing Table 22-14 Clock Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 738
EXTAL tDEXT tDEXT VCC STBY NMI tOSC1 tOSC1 RES ø Figure 22-37 Oscillator Settling Timing (2) Control Signal Timing Table 22-15 lists the control signal timing. Table 22-15 Control Signal Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 739
ø tRESS tRESS RES tRESW Figure 22-38 Reset Input Timing ø tNMIH tNMIS NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 22-39 Interrupt Input Timing Rev.6.00 Oct.28.
PAGE 740
(3) Bus Timing Table 22-16 lists the bus timing. Table 22-16 Bus Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø= 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item Test Symbol Min Max Unit Conditions Address delay time t AD — 20 ns Address setup time t AS 0.5 × t cyc – 15 — ns Figure 22-40 to Figure 22-47 Address hold time t AH 0.
PAGE 741
Condition Test Item Symbol Min Max Unit Conditions WR hold time t WCH 0.5 × t cyc – 10 — ns Figure 22-40 to Figure 22-47 CAS setup time t CSR 0.
PAGE 742
T1 T2 T3 ø tAD A23 to A0 tCSD1 tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 22-41 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.
PAGE 743
T1 T2 TW T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 22-42 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.
PAGE 744
Tp TC1 Tr TC2 ø tAD tAD A23 to A0 tAS tAH tPCH tCSD3 tACC4 CS5 to CS2 (RAS) tCSD2 tCASD tCASD tACC1 CAS tRDS tRDH tACC3 D15 to D0 (read) tWRD2 tWRD2 HWR, LWR (write) tWCS tWCH tWDH tWDD tWDS D15 to D0 (write) Figure 22-43 DRAM Bus Timing TRp TRr TRc1 TRc2 ø tCSD2 tCSD1 CS5 to CS2 (RAS) tCSR tCASD CAS Figure 22-44 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.
PAGE 745
TRp TRr TRc TRc ø tCSD2 tCSD2 CS5 to CS2 (RAS) tCASD tCASD CAS Figure 22-45 Self-Refresh Timing T1 T2 or T3 T1 T2 ø tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 22-46 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.
PAGE 746
T1 T2 or T3 T1 ø tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 22-47 Burst ROM Access Timing (One-State Access) ø tBRQS tBRQS BREQ tBACD tBACD BACK tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS Figure 22-48 External Bus Release Timing Rev.6.00 Oct.28.
PAGE 747
ø tBRQOD tBRQOD BREQO Figure 22-49 External Bus Request Output Timing (4) DMAC Timing Table 22-17 lists the DMAC timing. Table 22-17 DMAC Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 748
T1 T2 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK0 , DACK1 Figure 22-50 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.
PAGE 749
T1 T2 T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD2 tDACD1 DACK0, DACK1 Figure 22-51 DMAC Single Address Transfer Timing (Three-State Access) T1 T2 or T3 ø tTED tTED TEND0, TEND1 Figure 22-52 DMAC TEND Output Timing ø tDRQS tDRQH DREQ0, DREQ1 Figure 22-53 DMAC DREQ Intput Timing Rev.6.00 Oct.28.
PAGE 750
(5) Timing of On-Chip Supporting Modules Table 22-18 lists the timing of on-chip supporting modules. Table 22-18 Timing of On-Chip Supporting Modules Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 751
T1 T2 ø tPRS tPRH Ports 1 to 6, A to G (read) tPWD Ports 1 to 3, 5, 6, A to G (write) Figure 22-54 I/O Port Input/Output Timing ø tPOD PO15 to PO0 Figure 22-55 PPG Output Timing ø tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22-56 TPU Input/Output Timing Rev.6.00 Oct.28.
PAGE 752
ø tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 22-57 TPU Clock Input Timing ø tTMOD TMO0, TMO1 Figure 22-58 8-Bit Timer Output Timing ø tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 22-59 8-Bit Timer Clock Input Timing ø tTMRS TMRI0, TMRI1 Figure 22-60 8-Bit Timer Reset Input Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 22-61 SCK Clock Input Timing Rev.6.00 Oct.28.
PAGE 753
SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 22-62 SCI Input/Output Timing (Clock Synchronous Mode) ø tTRGS ADTRG Figure 22-63 A/D Converter External Trigger Input Timing 22.3.4 A/D Conversion Characteristics Table 22-19 lists the A/D conversion characteristics. Table 22-19 A/D Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 754
22.3.5 D/A Conversion Characteristics Table 22-20 lists the D/A conversion characteristics. Table 22-20 D/A Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) 22.3.6 Item Min Typ Max Unit Test Conditions Resolution 8 8 8 bits Conversion time — — 10 µs 20-pF capacitive load Absolute accuracy — ±1.0 ±1.
PAGE 755
Item Symbol Min Programming Wait time after SWE bit clear* 1 θ Erase 100 Typ Max — — Unit µs 5 Maximum programming count* 1* 4 N — — 1000* Times Wait time after SWE bit setting* 1 x 1 — — µs Wait time after ESU bit setting* 1 y 100 — — µs Wait time after E bit setting* 1* 6 z — — 10 ms α 10 — — µs 1 β 10 — — µs 1 γ 20 — — µs ε 2 — — µs η 4 — — µs θ 100 — — µs N — — 100 Times Wait time after E bit clear*1 Wait time after ESU bit clear* Wai
PAGE 756
Table 22-22 Flash Memory Characteristics (HD64F2398F20T, HD64F2398TE20T) Conditions: VCC = 5.0 V ± 10%, AV CC = 5.0 V ± 10%, Vref = 4.
PAGE 757
5. The maximum writing count (N) must be set to the maximum writing time (tP(max)) or less according the actual set value (z). Wait time (z) must be switched after setting of bit P according to writing count (n). Writing count n 1≤n≤6 z = 30 µs 7 ≤ n ≤ 1000 z = 200 µs [In additional writing] Writing count n 1≤n≤6 z = 10 µs 6. Wait time (z) after setting of bit E and the maximum erasing count (N) have the following relationship to the maximum erasing time (tE(max)).
PAGE 758
22.6 Electrical Characteristics of H8S/2357 Masked ROM and ZTAT Versions, and H8S/2352 22.6.1 Absolute Maximum Ratings Table 22-23 lists the absolute maximum ratings. Table 22-23 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +7.0 V Programming voltage* VPP –0.3 to +13.5 V Input voltage (except port 4) Vin –0.3 to VCC +0.3 V Input voltage (port 4) Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.
PAGE 759
Item Symbol Min Typ Max Unit VIL –0.3 — 0.5 V NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 –0.3 — 0.8 V Output high voltage All output pins VOH VCC – 0.5 — — V 3.5 — — V I OH = –1 mA Output low voltage All output pins VOL — — 0.4 V I OL = 1.6 mA Input leakage current RES Input low voltage Three-state leakage current (off state) RES, STBY, MD2 to MD0 Ports 1, A to C Current dissipation* 2 Analog power supply current — — 1.0 V I OL = 10 mA — 10.
PAGE 760
Table 22-24 DC Characteristics (2) Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol – Min Typ Max Unit VCC × 0.2 — — V — VCC × 0.7 V Test Conditions Port 2, P64 to P6 7, PA4 to PA 7 VT VT – VT VCC × 0.07 — — V RES, STBY, NMI, MD2 to MD0 VIH VCC × 0.9 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.
PAGE 761
Item Current dissipation* 2 Analog power supply current Symbol Min Typ — Sleep mode Standby mode* 3 Normal operation During A/D and D/A conversion I CC * 4 Al CC Idle Reference current During A/D and D/A conversion Al CC Idle RAM standby voltage VRAM Max Unit Test Conditions 23 62 (3.0 V) mA f = 10 MHz — 16 42 (3.0 V) mA f = 10 MHz — 0.01 5.0 µA Ta ≤ 50°C — — 20.0 — 0.2 2.0 (3.0 V) mA — 0.01 5.0 µA — 1.4 3.0 (3.0 V) mA — 0.01 5.0 µA 2.
PAGE 762
Item Symbol Min Typ Max Unit Test Conditions VCC – 0.5 — — V I OH = –200 µA VCC – 1.0 — — V I OH = –1 mA Output high voltage All output pins VOH Output low voltage All output pins VOL — — 0.4 V I OL = 1.6 mA Ports 1, A to C — — 1.0 V VCC ≤ 4.0 V I OL = 5 mA 4.0 < VCC ≤ 5.5 V I OL = 10 mA Input leakage current RES — — 10.0 µA STBY, NMI, MD2 to MD0 — — 1.0 µA Vin = 0.5 V to VCC – 0.5 V Port 4 — — 1.0 µA Vin = 0.5 V to AVCC – 0.5 V I TSI — — 1.
PAGE 763
Table 22-25 Permissible Output Currents Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Permissible output low current (per pin) Ports 1, A to C Permissible output low current (total) Total of 32 pins including ports 1 and A to C Symbol Min Typ Max Unit I OL — — 10 mA — — 2.
PAGE 764
22.6.3 AC Characteristics Figure 22-67 show, the test conditions for the AC characteristics. 5V RL C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G RL = 2.4 kΩ RH = 12 kΩ LSI output pin I/O timing test levels • Low level: 0.8 V • High level: 2.0 V RH C Figure 22-67 Output Load Circuit (1) Clock Timing Table 22-26 lists the clock timing Table 22-26 Clock Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.
PAGE 765
tcyc tCH tCf ø tCL tCr Figure 22-68 System Clock Timing EXTAL tDEXT tDEXT VCC STBY NMI tOSC1 tOSC1 RES ø Figure 22-69 Oscillator Settling Timing Rev.6.00 Oct.28.
PAGE 766
(2) Control Signal Timing Table 22-27 lists the control signal timing. Table 22-27 Control Signal Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 767
ø tNMIH tNMIS NMI tNMIW IRQi (i= 0 to 2) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 22-71 Interrupt Input Timing Rev.6.00 Oct.28.
PAGE 768
(3) Bus Timing Table 22-28 lists the bus timing. Table 22-28 Bus Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø= 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.
PAGE 769
Condition A Item Symbol Min WR pulse width 2 t WSW2 Max Condition B Min Max Condition C Min Max Test Unit Conditions 1.5 × — t cyc – 40 1.5 × — t cyc – 20 1.5 × — t cyc – 40 ns Write data delay time t WDD — — — 60 ns Write data setup time t WDS 0.5 × — t cyc – 40 0.5 × — t cyc – 20 0.5 × — t cyc – 33 ns Write data hold time t WDH 0.5 × — t cyc – 20 0.5 × — t cyc – 10 0.5 × — t cyc – 20 ns WR setup time t WCS 0.5 × — t cyc – 20 0.5 × — t cyc – 10 0.
PAGE 770
T1 T2 ø tAD A23 to A0 tCSD1 tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAS tAH tWDD tWSW1 tWDH D15 to D0 (write) Figure 22-72 Basic Bus Timing (Two-State Access) Rev.6.00 Oct.28.
PAGE 771
T1 T2 T3 ø tAD A23 to A0 tCSD1 tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 22-73 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.
PAGE 772
T1 T2 TW T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 22-74 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.
PAGE 773
Tp TC1 Tr TC2 ø tAD tAD A23 to A0 tAS tAH tPCH tCSD3 tACC4 CS5 to CS2 (RAS) tCSD2 tCASD tCASD tACC1 CAS tRDS tRDH tACC3 D15 to D0 (read) tWRD2 tWRD2 HWR, LWR (write) tWCS tWCH tWDH tWDD tWDS D15 to D0 (write) Figure 22-75 DRAM Bus Timing TRp TRr TRc1 TRc2 ø tCSD2 tCSD1 CS5 to CS2 (RAS) tCSR tCASD tCASD CAS Figure 22-76 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.
PAGE 774
TRp TRr TRc TRc ø tCSD2 tCSD2 CS5 to CS2 (RAS) tCASD tCASD CAS Figure 22-77 Self-Refresh Timing T1 T2 or T3 T1 T2 ø tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS D15 to D0 (read) Figure 22-78 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.
PAGE 775
T1 T2 or T3 T1 ø tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 22-79 Burst ROM Access Timing (One-State Access) ø tBRQS tBRQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS Figure 22-80 External Bus Release Timing Rev.6.00 Oct.28.
PAGE 776
ø tBRQOD tBRQOD BREQO Figure 22-81 External Bus Request Output Timing (4) DMAC Timing Table 22-29 lists the DMAC timing. Table 22-29 DMAC Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 777
T1 T2 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK0 , DACK1 Figure 22-82 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.
PAGE 778
T1 T2 T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD2 tDACD1 DACK0, DACK1 Figure 22-83 DMAC Single Address Transfer Timing (Three-State Access) T1 T2 or T3 ø tTED tTED TEND0, TEND1 Figure 22-84 DMAC TEND Output Timing ø tDRQS tDRQH DREQ0, DREQ1 Figure 22-85 DMAC DREQ Intput Timing Rev.6.00 Oct.28.
PAGE 779
(5) Timing of On-Chip Supporting Modules Table 22-30 lists the timing of on-chip supporting modules. Table 22-30 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 780
Condition A Condition B Condition C Symbol Min Max Min Max Min Test Max Unit Conditions Transmit data delay time t TXD — 100 — 50 — 75 ns Receive data setup time (synchronous) t RXS 100 — 50 — 75 — ns Receive data hold time (synchronous) t RXH 100 — 50 — 75 — ns t TRGS 50 — 30 — 50 — ns Item SCI A/D Trigger input setup con- time verter T1 T2 ø tPRS tPRH Ports 1 to 6, A to G (read) tPWD Ports 1 to 3, 5, 6, A to G (write) Figure 22-86 I/O Port Input/Output Timi
PAGE 781
ø tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22-88 TPU Input/Output Timing ø tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 22-89 TPU Clock Input Timing ø tTMOD TMO0, TMO1 Figure 22-90 8-Bit Timer Output Timing ø tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 22-91 8-Bit Timer Clock Input Timing Rev.6.00 Oct.28.
PAGE 782
ø tTMRS TMRI0, TMRI1 Figure 22-92 8-Bit Timer Reset Input Timing ø tWOVD tWOVD WDTOVF Figure 22-93 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 22-94 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 22-95 SCI Input/Output Timing (Clock Synchronous Mode) ø tTRGS ADTRG Figure 22-96 A/D Converter External Trigger Input Timing Rev.6.00 Oct.28.
PAGE 783
22.6.4 A/D Conversion Characteristics Table 22-31 lists the A/D conversion characteristics. Table 22-31 A/D Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 784
22.6.5 D/A Convervion Characteristics Table 22-32 lists the D/A conversion characteristics Table 22-32 D/A Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.
PAGE 785
22.7 Electrical Characteristics of H8S/2357 F-ZTAT Version 22.7.1 Absolute Maximum Ratings Table 22-33 lists the absolute maximum ratings. Table 22-33 Absolute Maximum Ratings Item Symbol Value Unit VCC –0.3 to +7.0 V Vin –0.3 to VCC +0.3 V Vin –0.3 to VCC +0.3 V Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.3 V Analog power supply voltage AVCC –0.3 to +7.0 V Analog input voltage VAN –0.3 to AVCC +0.
PAGE 786
Item Symbol Min Typ Max Unit — 0.8 V Test Conditions Input low voltage NMI, EXTAL, VIL Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 –0.3 Output high voltage All output pins VOH VCC – 0.5 — — V I OH = –200 µA 3.5 — — V I OH = –1 mA Output low voltage All output pins VOL — — 0.4 V I OL = 1.6 mA Ports 1, A to C — — 1.0 V I OL = 10 mA Input leakage current RES Vin = 0.5 V to VCC – 0.5 V Three-state leakage current (off state) — — 10.
PAGE 787
Table 22-34 DC Characteristics (2) Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Max Unit VT– VCC × 0.2 — — V VT+ — VCC × 0.7 V VT+ – VT– VCC × 0.07 — — V VIH VCC × 0.9 — VCC +0.3 V EXTAL VCC × 0.7 — VCC +0.3 V Ports 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 VCC × 0.7 — VCC +0.3 V Port 4 VCC × 0.7 — AVCC +0.3 V –0.
PAGE 788
Item Current dissipation* 2 Symbol Min Typ — Sleep mode Standby mode* 3 Normal operation I CC * 4 Flash memory programming/ erasing Analog power supply current During A/D and D/A conversion Al CC Idle Reference current During A/D and D/A conversion Al CC Idle Notes: 1. 2. 3. 4. Max Unit Test Conditions 32 80 (3.3 V) mA f = 13 MHz — 22 55 (3.3 V) mA f = 13 MHz — 0.01 5.0 µA Ta ≤ 50°C 20 0°C ≤ Ta ≤ 75°C f = 13 MHz — — — 42 80 (3.3 V) mA 50°C < Ta — 0.3 2.0 (3.
PAGE 789
22.7.3 AC Characteristics (1) Clock Timing Table 22-36 lists the clock timing Table 22-36 Clock Timing Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.
PAGE 790
(2) Control Signal Timing Table 22-37 lists the control signal timing. Table 22-37 Control Signal Timing Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.
PAGE 791
(3) Bus Timing Table 22-38 lists the bus timing. Table 22-38 Bus Timing Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø= 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.
PAGE 792
Condition B Condition C Item Symbol Min Max Min Max Unit Test Conditions Write data delay time t WDD — 30 — 60 ns Figure 22-72 to Figure 22-79 Write data setup time t WDS 0.5 × — t cyc – 20 0.5 × — t cyc – 36 ns Write data hold time t WDH 0.5 × — t cyc – 10 0.5 × — t cyc – 20 ns WR setup time t WCS 0.5 × — t cyc – 10 0.5 × — t cyc – 20 ns WR hold time t WCH 0.5 × — t cyc – 10 0.5 × — t cyc – 20 ns CAS setup time t CSR 0.5 × — t cyc – 10 0.
PAGE 793
(5) Timing of On-Chip Supporting Modules Table 22-40 lists the timing of on-chip supporting modules. Table 22-40 Timing of On-Chip Supporting Modules Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, Vref = 3.
PAGE 794
Condition B Symbol Min Max Min Max Unit Test Conditions Transmit data delay time t TXD — 50 — 75 ns Figure 22-95 Receive data setup time (synchronous) t RXS 50 — 75 — ns Receive data hold time (synchronous) t RXH 50 — 75 — ns t TRGS 30 — 50 — ns Item SCI A/D Trigger input setup converter time 22.7.4 Condition C Figure 22-96 A/D Conversion Characteristics Table 22-41 lists the A/D conversion characteristics.
PAGE 795
22.7.5 D/A Conversion Characteristics Table 22-42 lists the D/A conversion characteristics Table 22-42 D/A Conversion Characteristics Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = AVCC = 3.0 V to 5.5 V, Vref = 3.
PAGE 796
Item Symbol Min Programming Wait time after PV bit clear* 1η Erase 4 Typ Max — — Unit µs 5 Maximum programming count* 1* 4 N — — 1000* Times Wait time after SWE bit setting* 1 x 10 — — µs Wait time after ESU bit setting* 1 y 200 — — µs Wait time after E bit setting* 1* 6 z 5 — 10 ms Wait time after E bit clear*1 α 10 — — µs Wait time after ESU bit clear*1 β 10 — — µs Wait time after EV bit setting* 1 γ 20 — — µs Wait time after H’FF dummy ε write* 1 2 — —
PAGE 797
Item Symbol Min Typ Max Unit Programming Wait time after SWE bit setting* 1 x 10 — — µs Wait time after PSU bit setting* 1 y 50 — — µs Wait time after P bit setting* 1* 4 z 150 — 200 µs Wait time after P bit clear*1 α 10 — — µs Wait time after PSU bit clear*1 β 10 — — µs Wait time after PV bit setting* 1 γ 4 — — µs Wait time after H'FF dummy ε write* 1 2 — — µs Wait time after PV bit clear* 1 η 4 — — µs Maximum programming count* 1* 4 N — — 1000 Times *
PAGE 798
22.8 Usage Note Although the ZTAT, F-ZTAT, and masked ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is evaluated using the ZTAT and F-ZTAT versions, a similar evaluation should also be performed using the masked ROM version.
PAGE 799
Appendix A Instruction Set A.
PAGE 800
Rev.6.00 Oct.28.2004 page 770 of 1016 REJ09B0138-0600H MOV B B B B B B B W 4 W W MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd B MOV.B @aa:32,Rd MOV.B Rs,@ERd B MOV.B @aa:16,Rd B MOV.B @(d:32,ERs),Rd B B MOV.B @(d:16,ERs),Rd B B MOV.B @ERs,Rd MOV.B @aa:8,Rd B MOV.B Rs,Rd MOV.B @ERs+,Rd B 2 MOV.
PAGE 801
Rev.6.00 Oct.28.2004 page 771 of 1016 REJ09B0138-0600H MOV L MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd L L MOV.L @ERs,ERd MOV.L @aa:32,ERd L MOV.L ERs,ERd L L MOV.L #xx:32,ERd L L 6 MOV.W Rs,@aa:32 MOV.L @aa:16,ERd W MOV.W Rs,@aa:16 MOV.L @ERs+,ERd W W MOV.W Rs,@-ERd W MOV.W Rs,@(d:32,ERd) W MOV.W @aa:32,Rd W W MOV.W @aa:16,Rd W W MOV.W @ERs+,Rd MOV.W Rs,@(d:16,ERd) W MOV.W @(d:32,ERs),Rd MOV.
PAGE 802
Rev.6.00 Oct.28.
PAGE 803
Rev.6.00 Oct.28.2004 page 773 of 1016 REJ09B0138-0600H B B W 4 SUB.B Rs,Rd SUB.W #xx:16,Rd W INC.W #2,Rd DAA Rd W INC.W #1,Rd SUB B INC.B Rd DAA L ADDS #4,ERd L L ADDS #2,ERd INC.L #2,ERd L ADDS #1,ERd L B ADDX Rs,Rd ADD.L #xx:32,ERd L L 6 ADD.W Rs,Rd B 2 W ADD.W #xx:16,Rd ADDX #xx:8,Rd W 4 ADD.B Rs,Rd ADD.L ERs,ERd B ADD.B #xx:8,Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 B 2 Mnemonic INC.
PAGE 804
L B 2 B L L L B W W L L B B W B W SUB.L ERs,ERd SUBX #xx:8,Rd SUBX Rs,Rd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS.B Rs,Rd MULXS.W Rs,ERd DAS MULXU MULXS DEC SUBS SUBX L 6 SUB.L #xx:32,ERd 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 W SUB.
PAGE 805
Rev.6.00 Oct.28.2004 page 775 of 1016 REJ09B0138-0600H EXTU NEG CMP DIVXS DIVXU B 2 B W 4 W L 6 L CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd L W L NEG.L ERd EXTU.W Rd EXTU.L ERd B W DIVXS.W Rs,ERd W B divxs.B Rs,Rd NEG.W Rd W DIVXU.W Rs,ERd NEG.B Rd B DIVXU.
PAGE 806
Rev.6.00 Oct.28.2004 page 776 of 1016 REJ09B0138-0600H MAC @ERn+, @ERm+ CLRMAC LDMAC ERs,MACH MAC CLRMAC LDMAC STMAC TAS @ERd*3 TAS STMAC MACL,ERd STMAC MACH,ERd LDMAC ERs,MACL B EXTS.L ERd Operation ( of @ERd) @ERd-0→CCR set, (1)→ ( of ERd32) ( of ERd32)→ ( of Rd16) ( of Rd16)→ Cannot be used in the H8S/2357 Group 2 4 L EXTS.
PAGE 807
Rev.6.00 Oct.28.2004 page 777 of 1016 REJ09B0138-0600H NOT XOR OR AND L 6 L OR.L #xx:32,ERd OR.L ERs,ERd B W L NOT.W Rd NOT.L ERd L NOT.B Rd L 6 XOR.W Rs,Rd XOR.L ERs,ERd W XOR.W #xx:16,Rd XOR.L #xx:32,ERd B W 4 XOR.B Rs,Rd B 2 W OR.W Rs,Rd XOR.B #xx:8,Rd W 4 L AND.L ERs,ERd OR.W #xx:16,Rd L 6 AND.L #xx:32,ERd B W AND.W Rs,Rd B 2 W 4 AND.W #xx:16,Rd OR.B Rs,Rd B OR.B #xx:8,Rd B 2 AND.B Rs,Rd 2 2 2 4 2 2 4 2 2 4 2 2 Operand Size #xx Rn AND.
PAGE 808
Rev.6.00 Oct.28.2004 page 778 of 1016 REJ09B0138-0600H SHLL SHAR SHAL W W L L SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd B L SHAR.L #2,ERd B L SHAR.L ERd SHLL.B #2,Rd W SHAR.W #2,Rd SHLL.B Rd W SHAR.W Rd SHAL.L #2,ERd B L SHAL.L ERd B L SHAL.W #2,Rd SHAR.B #2,Rd W SHAL.W Rd SHAR.B Rd B W SHAL.B #2,Rd B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — SHAL.
PAGE 809
Rev.6.00 Oct.28.2004 page 779 of 1016 REJ09B0138-0600H ROTXR ROTXL SHLR W W L L SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL.L #2,ERd W W L L ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd B L ROTXL.L ERd ROTXR.B #2,Rd L ROTXL.W #2,Rd B W ROTXL.W Rd ROTXR.B Rd B W ROTXL.B #2,Rd B B SHLR.B #2,Rd ROTXL.B Rd B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — SHLR.
PAGE 810
Rev.6.00 Oct.28.2004 page 780 of 1016 REJ09B0138-0600H ROTR ROTL W W L L ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd L ROTL.L #2,ERd B L ROTL.L ERd ROTR.B #2,Rd W ROTL.W #2,Rd B W ROTL.W Rd ROTR.B Rd B B ROTL.B #2,Rd 2 2 2 2 2 2 2 2 2 2 2 2 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ROTL.
PAGE 811
Rev.6.00 Oct.28.
PAGE 812
BTST B B B BTST #xx:3,@aa:16 B BTST #xx:3,Rd BTST #xx:3,@aa:8 B BNOT Rn,@aa:32 BTST #xx:3,@ERd B BNOT Rn,Rd BNOT Rn,@aa:16 B BNOT #xx:3,@aa:32 B B BNOT #xx:3,@aa:16 B B BNOT #xx:3,@aa:8 BNOT Rn,@aa:8 B BNOT #xx:3,@ERd BNOT Rn,@ERd B BNOT #xx:3,Rd BNOT 2 2 4 4 4 B BCLR Rn,@aa:32 BCLR 6 4 8 6 4 8 6 4 8 B Mnemonic 2 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Addressing Mode/ Instruction Length (Bytes) 4 5 6 1 4 4 5 6 — — — — — — — — —
PAGE 813
Rev.6.00 Oct.28.
PAGE 814
Rev.6.00 Oct.28.
PAGE 815
Rev.6.00 Oct.28.
PAGE 816
Rev.6.00 Oct.28.
PAGE 817
Rev.6.00 Oct.28.
PAGE 818
Rev.6.00 Oct.28.
PAGE 819
Rev.6.00 Oct.28.
PAGE 820
NOP XORC ORC ANDC STC W W W B 2 B 4 B 2 B 4 B 2 B 4 — STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC #xx:8,CCR ANDC #xx:8,EXR ORC #xx:8,CCR ORC #xx:8,EXR XORC #xx:8,CCR XORC #xx:8,EXR NOP 10 10 6 4 8 8 6 2 1 — — — — — — EXR∨#xx:8→EXR CCR⊕#xx:8→CCR — — — — — — — — — — — — EXR⊕#xx:8→EXR 1 2 2 1 — — — — — — 5 — — — — — — EXR→@aa:32 CCR∨#xx:8→CCR 5 — — — — — — CCR→@aa:32 EXR∧#xx:8→EXR 4 — — — — — — EXR→@aa:16 1 4 CCR∧#xx:8→CCR 4 EXR→@(d:32,ERd) — — — — — — 6 — — — —
PAGE 821
Rev.6.00 Oct.28.2004 page 791 of 1016 REJ09B0138-0600H Addressing Mode/ Instruction Length (Bytes) — — EEPMOV.B EEPMOV.W — — — — — — 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; I H N Z V C — — — — — — 4 if R4L≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; Operation Condition Code 4+2n *2 4+2n *2 Advanced No. of States*1 Notes: 1.
PAGE 822
Rev.6.00 Oct.28.2004 page 792 of 1016 REJ09B0138-0600H Bcc BAND ANDC AND ADDX ADDS ADD Instruction 0 5 4 5 — — — BRN d:8 (BF d:8) BRN d:16 (BF d:16) 6 B BAND #xx:3,@aa:32 BRA d:16 (BT d:16) 6 B BAND #xx:3,@aa:16 4 7 B BAND #xx:3,@aa:8 — 7 B BAND #xx:3,@ERd BRA d:8 (BT d:8) 7 B 0 BAND #xx:3,Rd 0 0 L AND.L ERs,ERd B 7 L AND.L #xx:32,ERd B 6 W AND.W Rs,Rd ANDC #xx:8,EXR 7 AND.W #xx:16,Rd ANDC #xx:8,CCR 1 B W AND.B Rs,Rd E B B ADDX Rs,Rd AND.
PAGE 823
Rev.6.00 Oct.28.
PAGE 824
Rev.6.00 Oct.28.
PAGE 825
Rev.6.00 Oct.28.
PAGE 826
Rev.6.00 Oct.28.
PAGE 827
Rev.6.00 Oct.28.2004 page 797 of 1016 REJ09B0138-0600H W W L L DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd — — EEPMOV.W B W DIVXU.W Rs,ERd W DIVXS.W Rs,ERd DIVXU.B Rs,Rd B DIVXS.B Rs,Rd EEPMOV EEPMOV.B DIVXU DIVXS B DEC.B Rd B DEC L CMP.L ERs,ERd B L CMP.L #xx:32,ERd DAS Rd W CMP.W Rs,Rd DAA Rd W CMP.W #xx:16,Rd DAS B DAA B CMP.B Rs,Rd B BXOR #xx:3,@aa:32 CMP.
PAGE 828
Rev.6.00 Oct.28.2004 page 798 of 1016 REJ09B0138-0600H LDC JSR JMP INC EXTU EXTS Instruction 0 0 0 0 0 0 0 0 0 0 0 B W W W W W W W W W W LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR 0 B LDC Rs,CCR LDC @ERs,CCR 0 B LDC Rs,EXR 0 B 5 — JSR @@aa:8 LDC #xx:8,EXR 5 — LDC #xx:8,CCR 5 — JSR @aa:24 5 — JMP @@aa:8 JSR @ERn 5 — 0 L INC.L #2,ERd JMP @aa:24 0 L INC.
PAGE 829
Rev.6.00 Oct.28.2004 page 799 of 1016 REJ09B0138-0600H B B B B B B B B B B B B B B B B W W W W W MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.
PAGE 830
Rev.6.00 Oct.28.2004 page 800 of 1016 REJ09B0138-0600H 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 W W W L L L L L L L L L L L L B B MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 L L MOV.W Rs,@-ERd MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXU MULXS B W MULXU.
PAGE 831
Rev.6.00 Oct.28.2004 page 801 of 1016 REJ09B0138-0600H 6 7 0 W L L OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ROTL PUSH POP ORC 1 1 1 1 1 B W W L L ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd 1 0 L B PUSH.L ERn ROTL.B Rd 6 0 L W POP.L ERn PUSH.W Rn 6 W POP.W Rn 0 7 W OR.W #xx:16,Rd 0 1 B OR.B Rs,Rd B C B OR.B #xx:8,Rd B 1 L NOT.L ERd ORC #xx:8,EXR 1 W NOT.W Rd ORC #xx:8,CCR 1 B OR 0 — NOT.B Rd 1 L NEG.L ERd NOP 1 W NEG.
PAGE 832
Rev.6.00 Oct.28.2004 page 802 of 1016 REJ09B0138-0600H 1 B SHAL.B Rd 1 1 1 1 1 B W W L L SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd 5 SHAL — RTS 1 L ROTXR.L #2, ERd RTS 1 L ROTXR.L ERd 5 1 W ROTXR.W #2, Rd — 1 W ROTXR.W Rd RTE 1 B 1 L ROTXL.L #2, ERd ROTXR.B #2, Rd 1 L ROTXL.L ERd 1 1 W ROTXL.W #2, Rd B 1 W ROTXL.W Rd ROTXR.B Rd 1 B 1 L ROTR.L #2, ERd ROTXL.B #2, Rd 1 L ROTR.L ERd 1 1 W ROTR.W #2, Rd B 1 ROTR.W Rd ROTXL.
PAGE 833
Rev.6.00 Oct.28.2004 page 803 of 1016 REJ09B0138-0600H 0 0 0 0 0 0 0 W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W W STC.W CCR,@ERd STC.W CCR,@-ERd STC.W EXR,@-ERd 0 0 B W STC.B EXR,Rd 0 B STC.B CCR,Rd 1 L SHLR.L #2, ERd STC 1 L SHLR.L ERd 0 1 W SHLR.W #2, Rd — 1 W SHLR.W Rd SLEEP 1 B 1 L SHLL.L #2, ERd SHLR.B #2, Rd 1 L SHLL.L ERd 1 1 W SHLL.W #2, Rd B 1 W SHLL.W Rd SHLR.
PAGE 834
Rev.6.00 Oct.28.2004 page 804 of 1016 REJ09B0138-0600H L SUBS #4,ERd B B — B B W W L L SUBX Rs,Rd TAS @ERd*2 TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd TRAPA XOR B L SUBX #xx:8,Rd L SUBS #2,ERd L SUBS #1,ERd L L STMAC MACL,ERd SUB.L ERs,ERd L STMAC MACH,ERd SUB.L #xx:32,ERd L STM.L (ERn-ERn+3), @-SP W L STM.L (ERn-ERn+2), @-SP SUB.W Rs,Rd L STM.L(ERn-ERn+1), @-SP W W STC.W EXR,@aa:32 SUB.W #xx:16,Rd W STC.
PAGE 835
Rev.6.00 Oct.28.
PAGE 836
Rev.6.00 Oct.28.2004 page 806 of 1016 REJ09B0138-0600H AL 2 BH 3 BL 2nd byte XOR BSR BCS AND RTE BNE BST TRAPA BEQ MOV AND D E MOV OR XOR C CMP SUBX B F SUB ADD BVS 9 Table A.3(2) MOV Table A.3(2) A Note: * Cannot be used in the H8S/2357 Group. 8 BVC MOV.B Table A.3(2) LDC 7 BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD OR RTS BCC AND ANDC 6 ADDX BTST DIVXU BLS XOR XORC 5 9 BCLR MULXU BHI OR ORC 4 Table A.3(2) Table A.3(2) JMP BPL Table A.
PAGE 837
Rev.6.00 Oct.28.2004 page 807 of 1016 REJ09B0138-0600H BRA MOV MOV MOV 58 6A 79 7A ADD CMP CMP MOV ADD BHI BRN 2 BH Table A.3(4) AL BCC ROTXR ROTXL SHLR SHLL STC 4 LDC SUB SUB OR OR Table * A.3(4) MOVFPE BLS NOT STM 3 BL 2nd byte Note: * Cannot be used in the H8S/2357 Group.
PAGE 838
Rev.6.00 Oct.28.2004 page 808 of 1016 REJ09B0138-0600H BCLR MULXS 2 3 BSET 7Faa7 *2 BNOT BNOT BCLR BCLR Notes: 1. r is the register specification field. 2. aa is the absolute address specification.
PAGE 839
Rev.6.00 Oct.28.2004 page 809 of 1016 REJ09B0138-0600H BSET 0 AH BNOT 1 AL 1st byte BNOT 1 0 BSET AL AH 1st byte BCLR 2 BH 3 3 6 DL 7 EH EL 5th byte 5 DH 6 DL 4th byte 7 EH EL 5th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 5 DH 4th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 2nd byte BCLR 2 BH 2nd byte Note: * aa is the absolute address specification.
PAGE 840
A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle.
PAGE 841
Table A-5 Number of Cycles in Instruction Execution Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I ADD ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd 1 AND ANDC BAND Bcc ADDX Rs,Rd 1 AND.B #xx:8,Rd 1 J K L AND.B Rs,Rd 1 AND.W #xx:16,Rd 2 AND.W Rs,Rd 1 AND.L #xx:32,ERd 3 AND.
PAGE 842
Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I Bcc BLS d:16 2 1 BCC d:16 (BHS d:16) 2 1 BCS d:16 (BLO d:16) 2 1 BCLR BIAND BILD BIOR BIST J K L BNE d:16 2 1 BEQ d:16 2 1 BVC d:16 2 1 BVS d:16 2 1 BPL d:16 2 1 BMI d:16 2 1 BGE d:16 2 1 BLT d:16 2 1 BGT d:16 2 1 BLE d:16 2 1 BCLR #xx:3,Rd 1 BCLR #xx:3,@ERd 2 2 BCLR #xx:3,@aa:8 2 2 BCLR #xx:3,@aa:16 3 2 BCLR
PAGE 843
Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I BIXOR BIXOR #xx:3,Rd 1 BLD BNOT BOR BSET BSR BST J K L BIXOR #xx:3,@ERd 2 1 BIXOR #xx:3,@aa:8 2 1 BIXOR #xx:3,@aa:16 3 1 BIXOR #xx:3,@aa:32 4 1 BLD #xx:3,Rd 1 BLD #xx:3,@ERd 2 1 BLD #xx:3,@aa:8 2 1 BLD #xx:3,@aa:16 3 1 BLD #xx:3,@aa:32 4 1 BNOT #xx:3,Rd 1 BNOT #xx:3,@ERd 2 2 BNOT #xx:3,@aa:8 2 2 BNOT #xx:3,@aa:16 3 2 BN
PAGE 844
Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I BTST BTST #xx:3,Rd 1 BXOR J K L BTST #xx:3,@ERd 2 1 BTST #xx:3,@aa:8 2 1 BTST #xx:3,@aa:16 3 1 BTST #xx:3,@aa:32 4 1 BTST Rn,Rd 1 BTST Rn,@ERd 2 1 BTST Rn,@aa:8 2 1 BTST Rn,@aa:16 3 1 BTST Rn,@aa:32 4 1 BXOR #xx:3,Rd 1 BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 BXOR #xx:3,@aa:16 3 1 1 BXOR #xx:3,@aa:32 4 CLRMAC CLRMAC Cann
PAGE 845
Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I JMP JMP @ERn 2 JMP @aa:24 2 JSR LDC LDM LDMAC J K L 1 JMP @@aa:8 Advanced 2 JSR @ERn Advanced 2 2 2 JSR @aa:24 Advanced 2 2 JSR @@aa:8 Advanced 2 LDC #xx:8,CCR 1 LDC #xx:8,EXR 2 LDC Rs,CCR 1 LDC Rs,EXR 1 LDC @ERs,CCR 2 1 LDC @ERs,EXR 2 1 LDC @(d:16,ERs),CCR 3 1 LDC @(d:16,ERs),EXR 3 1 LDC @(d:32,ERs),CCR 5 1 LDC @(d:32,E
PAGE 846
Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I MOV MOV.B Rs,@-ERd 1 1 MOV.B Rs,@aa:8 1 1 MOV.B Rs,@aa:16 2 1 MOV.B Rs,@aa:32 3 1 MOV.W #xx:16,Rd 2 MOV.W Rs,Rd 1 MOV.W @ERs,Rd 1 1 MOV.W @(d:16,ERs),Rd 2 1 MOV.W @(d:32,ERs),Rd 4 1 MOV.W @ERs+,Rd 1 1 MOV.W @aa:16,Rd 2 1 MOV.W @aa:32,Rd 3 1 MOV.W Rs,@ERd 1 1 MOV.W Rs,@(d:16,ERd) 2 1 MOV.W Rs,@(d:32,ERd) 4 1 MOV.
PAGE 847
Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I NOT NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR.B #xx:8,Rd 1 OR.B Rs,Rd 1 OR.W #xx:16,Rd 2 OR.W Rs,Rd 1 OR.L #xx:32,ERd 3 OR.L ERs,ERd 2 ORC #xx:8,CCR 1 ORC #xx:8,EXR 2 POP.W Rn 1 1 1 POP.L ERn 2 2 1 PUSH.W Rn 1 1 1 PUSH.L ERn 2 2 1 ROTL.B Rd 1 OR ORC POP PUSH ROTL ROTR ROTL.B #2,Rd 1 ROTL.W Rd 1 ROTL.W #2,Rd 1 ROTL.
PAGE 848
Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I SHAL SHAL.B Rd 1 SHAR SHLL SHLR SHAL.B #2,Rd 1 SHAL.W Rd 1 SHAL.W #2,Rd 1 SHAL.L ERd 1 SHAL.L #2,ERd 1 SHAR.B Rd 1 SHAR.B #2,Rd 1 SHAR.W Rd 1 SHAR.W #2,Rd 1 SHAR.L ERd 1 SHAR.L #2,ERd 1 SHLL.B Rd 1 SHLL.B #2,Rd 1 SHLL.W Rd 1 SHLL.W #2,Rd 1 SHLL.L ERd 1 SHLL.L #2,ERd 1 SHLR.B Rd 1 SHLR.B #2,Rd 1 SHLR.W Rd 1 SHLR.
PAGE 849
Branch Byte Instruction Address Stack Data Fetch Read Operation Access Word Data Access Internal Operation M N Instruction Mnemonic I STM STM.L (ERn-ERn+1), @-SP 2 4 1 STM.L (ERn-ERn+2), @-SP 2 6 1 STM.L (ERn-ERn+3), @-SP 2 8 1 STMAC MACH,ERd Cannot be used in the H8S/2357 Group STMAC J K L STMAC MACL,ERd SUB SUB.B Rs,Rd 1 SUB.W #xx:16,Rd 2 SUB.W Rs,Rd 1 SUB.L #xx:32,ERd 3 SUB.
PAGE 850
A.5 Bus States during Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle.
PAGE 851
Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states.
PAGE 852
Rev.6.00 Oct.28.2004 page 822 of 1016 REJ09B0138-0600H Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.
PAGE 853
Rev.6.00 Oct.28.
PAGE 854
Rev.6.00 Oct.28.
PAGE 855
Rev.6.00 Oct.28.
PAGE 856
Rev.6.00 Oct.28.
PAGE 857
Rev.6.00 Oct.28.2004 page 827 of 1016 REJ09B0138-0600H 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.
PAGE 858
Rev.6.00 Oct.28.2004 page 828 of 1016 REJ09B0138-0600H R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@–ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.
PAGE 859
Rev.6.00 Oct.28.2004 page 829 of 1016 REJ09B0138-0600H MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.
PAGE 860
Rev.6.00 Oct.28.2004 page 830 of 1016 REJ09B0138-0600H 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.
PAGE 861
Rev.6.00 Oct.28.2004 page 831 of 1016 REJ09B0138-0600H R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 3rd Internal operation:M W:W EA W:W EA R:W NEXT R:W:M stack (H) R:W stack (L) Advanced R:W NEXT SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.
PAGE 862
Rev.6.00 Oct.28.2004 page 832 of 1016 REJ09B0138-0600H R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.
PAGE 863
Rev.6.00 Oct.28.2004 page 833 of 1016 REJ09B0138-0600H 7. 8. 3. 4. 5. 6. Notes: 1. 2. R:W*6 1 R:W 2nd R:W NEXT R:W 2nd R:W VEC 3 4 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state R:W NEXT R:W VEC+2 2 R:W NEXT W:W stack (EXR) 5 R:W:M VEC 6 R:W VEC+2 7 9 Internal operation, R:W*7 1 state 8 EAs is the contents of ER5. EAd is the contents of ER6. EAs is the contents of ER5. EAd is the contents of ER6.
PAGE 864
A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below.
PAGE 865
Table A-7 Condition Code Modification Instruction H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADD N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADDX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm AND — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ANDC Stores the corresponding bits of the result.
PAGE 866
Instruction H DAA * N Z V C Definition N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm DIVXS — — — N = Sm · Dm + Sm · Dm Z = Sm · Sm–1 · ...... · S0 DIVXU — — — N = Sm Z = Sm · Sm–1 · ...... · S0 EEPMOV — — — — — EXTS — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 EXTU — 0 INC — 0 — Z = Rm · Rm–1 · ......
PAGE 867
Instruction H NOT — N Z V C Definition 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 OR — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ORC Stores the corresponding bits of the result. No flags change when the operand is EXR. POP — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 PUSH — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ROTL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTR — 0 N = Rm Z = Rm · Rm–1 · ......
PAGE 868
Instruction H N Z V C Definition STMAC Cannot be used in the H8S/2357 Group SUB H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUBX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS — 0 — N = Dm Z = Dm · Dm–1 · ...... · D0 TRAPA — — — — — XOR — 0 — N = Rm Z = Rm · Rm–1 · ......
PAGE 869
Appendix B Internal I/O Register B.
PAGE 870
Address Register (low) Name Bit 7 Bit 6 Bit 5 Bit 4 H’FEA0 TCR5 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 H’FEA1 TMDR5 — — — — MD3 MD2 MD1 MD0 H’FEA2 TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H’FEA4 TIER5 TTGE — TCIEU TCIEV — — TGIEB TGIEA H’FEA5 TSR5 TCFD — TCFU TCFV — — TGFB TGFA H’FEA6 TCNT5 — Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width TPSC1 TPSC0 TPU5 16 bits Port 8 bits Interrupt controller 8 bits Bus controller 8 bits H’FEA7 H’FEA8 T
PAGE 871
Address Register (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FEE0 — — — — — — — DMAC 16 bits — — — — — — — — — — — — — — DMAC 16 bits — — — — — — — MAR0AH — H’FEE1 H’FEE2 MAR0AL H’FEE3 H’FEE4 IOAR0A H’FEE5 H’FEE6 ETCR0A H’FEE7 H’FEE8 MAR0BH — H’FEE9 H’FEEA MAR0BL H’FEEB H’FEEC IOAR0B H’FEED H’FEEE ETCR0B H’FEEF H’FEF0 MAR1AH — H’FEF1 H’FEF2 MAR1AL H’FEF3 H’FEF4 IOAR1A H’FEF5 H’FEF6 ETCR1A H’FEF7 H’F
PAGE 872
Address Register (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H’FF06 DMABCRH FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Short address mode FAE1 FAE0 — — DTA1 — DTA0 — Full address mode DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Short address mode DTIE1B DTIE1A DTIE0B DTIE0A Full address mode H’FF07 DMABCRL DTE1B DTME1 DTE1 H’FF2C ISCRH DTME0 DTE0 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt controller H’FF2D
PAGE 873
Address Register (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H’FF5E PORTF PF6 PF5 PF4 PF3 PF2 PF1 PF0 Port 8 bits H’FF5F PORTG — — — PG4 PG3 PG2 PG1 PG0 H’FF60 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR H’FF61 P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR H’FF62 P3DR — — P35DR P34DR P33DR P32DR P31DR P30DR H’FF64 P5DR — — — — P53DR P52DR P51DR P50DR H’FF65 P6DR P67DR P66DR P6
PAGE 874
Address Register (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H’FF8C RDRF ORER FER/ PER TEND MPB MPBT SSR2 TDRE ERS*5 Module Name Data Bus Width SCI2, 8 bits Smart Card interface 2 H’FF8D RDR2 H’FF8E SCMR2 — — — SDIR SINV — SMIE H'FF90 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FF91 ADDRAL AD1 AD0 — — — — — — H'FF92 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'FF93 ADDRBL AD1 AD0 — — — — — — H'FF94 ADDRCH AD9 AD8 AD7 AD6 AD5
PAGE 875
Address Register (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Module Name Data Bus Width H’FFD0 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU0 16 bits H’FFD1 TMDR0 — — H’FFD2 TIOR0H IOB3 IOB2 BFB BFA MD3 MD2 MD1 MD0 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H’FFD3 TIOR0L IOD3 H’FFD4 TIER0 TTGE IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 — — TCIEV TGIED TGIEC TGIEB TGIEA H’FFD5 TSR0 H’FFD6 TCNT0 — — — TCFV TGFD TGFC TGFB TGFA — CCLR1 CCLR0 CKEG1
PAGE 876
6. Applies to the H8S/2357 ZTAT only. 7. Applies to the H8S/2357 F-ZTAT only. 8. Applies to the H8S/2398 F-ZTAT only. Rev.6.00 Oct.28.
PAGE 877
B.
PAGE 878
MRB—DTC Mode Register B Bit : Initial value : H'F800—H'FBFF DTC 7 6 5 4 3 2 1 0 CHNE DISEL — — — — — — Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write : — — — — — — — — Reserved Only 0 should be written to these bits DTC Interrupt Select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Enable 0 End of DTC data
PAGE 879
CRB—DTC Transfer Count Register B Bit : Initial value : Read/Write : 15 14 H'F800—H'FBFF 13 12 11 10 9 8 7 DTC 6 5 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — Specifies the number of DTC block data transfers TCR3—Timer Control Register 3 Bit : H'FE80 7 6 5 TPU3 4 3 2 1 0 TPS
PAGE 880
TMDR3—Timer Mode Register 3 H'FE81 TPU3 7 6 5 4 3 2 1 0 — — BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Bit : Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — × : Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2.
PAGE 881
TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3 7 6 5 4 3 2 1 0 Initial value : IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit : TGR3A I/O Control 0 0 0 0 1 1 0 TGR3A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match 1 1 0 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 0 output at compare
PAGE 882
TIOR3L—Timer I/O Control Register 3L Bit H'FE83 TPU3 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TRG3C I/O Control 0 0 0 1 1 0 1 0 TGR3C Output disabled is output 1 compare Initial output is 0 output 0 register 1 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 1 0 output at compare match 0 output a
PAGE 883
TIER3—Timer Interrupt Enable Register 3 H'FE84 TPU3 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — — R/W R/W R/W R/W R/W Bit : TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 Interrupt req
PAGE 884
TSR3—Timer Status Register 3 Bit H'FE85 TPU3 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA : Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions]
PAGE 885
TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D Bit : 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCR4—Timer Control Register 4 Bit : TPU3 TPU3 TPU3 TPU3 15 Initial value : Read/Write : H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 7 6 5 — CCLR1 CCLR0 4 TPU4 3 CKEG1 CKEG0 2 1 0 TPSC2 TPSC1 TPSC0 Ini
PAGE 886
TMDR4—Timer Mode Register 4 H'FE91 TPU4 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Bit : Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — × : Don’t care Note: Rev.6.00 Oct.28.2004 page 856 of 1016 REJ09B0138-0600H MD3 is a reserved bit.
PAGE 887
TIOR4—Timer I/O Control Register 4 Bit H'FE92 TPU4 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR4A I/O Control 0 0 0 1 1 0 1 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 0 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 × × × 1 output at compare
PAGE 888
TIER4—Timer Interrupt Enable Register 4 Bit : H'FE94 TPU4 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 Interrupt requests
PAGE 889
TSR4—Timer Status Register 4 Bit H'FE95 TPU4 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA : Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • Whe
PAGE 890
TGR4A—Timer General Register 4A TGR4B—Timer General Register 4B Bit H'FE98 H'FE9A TPU4 TPU4 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCR5—Timer Control Register 5 H'FEA0 7 6 5 — CCLR1 CCLR0 Initial value : 0 0 0 0 Read/Write : — R/W R/W R/W Bit : 4 TPU5 3 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 0 R/W R/W R/W R/W CKEG1 CK
PAGE 891
TMDR5—Timer Mode Register 5 H'FEA1 TPU5 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Bit : Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — × : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Oct.28.
PAGE 892
TIOR5—Timer I/O Control Register 5 Bit H'FEA2 TPU5 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR5A I/O Control 0 0 0 1 1 0 1 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 × 0 1 0 TGR5A is input 1 capture × registe
PAGE 893
TIER5—Timer Interrupt Enable Register 5 Bit : H'FEA4 TPU5 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 Interrupt requests
PAGE 894
TSR5—Timer Status Register 5 Bit : H'FEA5 TPU5 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • Whe
PAGE 895
TGR5A—Timer General Register 5A TGR5B—Timer General Register 5B Bit H'FEA8 H'FEAA TPU5 TPU5 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P1DDR—Port 1 Data Direction Register Bit H'FEB0 7 : 6 5 Port 1 4 3 2 0 1 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W
PAGE 896
P6DDR—Port 6 Data Direction Register Bit : 7 H'FEB5 6 5 Port 6 4 3 2 0 1 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or output for individual port 6 pins PADDR—Port A Data Direction Register Bit : 7 H'FEB9 6 Port A 5 4 3 2 0 1 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or out
PAGE 897
PDDDR—Port D Data Direction Register Bit 7 : H'FEBC 6 5 Port D [On-chip ROM version Only] 4 3 2 1 0 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or output for individual port D pins PEDDR—Port E Data Direction Register Bit : 7 H'FEBD 6 5 Port E 4 3 2 1 0 PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W
PAGE 898
IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK — — — — — — — — — — — Interrupt Priority Register A Interrupt Priority Register B Interrupt Priority Register C Interrupt Priority Register D Interrupt Priority Register E Interrupt Priority Register F Interrupt Priority Register G Interrupt Priority Register H Interrupt Priority Register I Interrupt Priority Register J Interrupt Priority Register K Bit : H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE Interrupt Control
PAGE 899
ABWCR—Bus Width Control Register Bit H'FED0 Bus Controller 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W : Modes 5 to 7 Initial value : R/W : Mode 4 Area 7 to 0 Bus Width Control 0 Area n is designated for 16-bit access 1 Area n is designated for 8-bit access (n = 7 to 0) Note: * Modes 6 and 7 are provided in the O
PAGE 900
WCRH—Wait Control Register H Bit : H'FED2 Bus Controller 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Area 4 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 5 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 pr
PAGE 901
WCRL—Wait Control Register L Bit : H'FED3 Bus Controller 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Area 0 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 1 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 pr
PAGE 902
BCRH—Bus Control Register H Bit : H'FED4 7 6 ICIS1 ICIS0 5 Bus Controller 4 3 1 0 RMTS1 RMTS0 2 BRSTRM BRSTS1 BRSTS0 RMTS2 Initial value : 1 1 0 1 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W RAM Type Select RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 1 1 — 0 Normal space 1 Normal space 0 Normal space DRAM space DRAM space 1 DRAM space — — Note: When areas selected in DRAM space are all 8-bit space, the PF2 pin can be used as an I/O port, BRE
PAGE 903
BCRL—Bus Control Register L Bit H'FED5 Bus Controller 7 6 5 4 3 2 1 0 BRLE BREQOE EAE LCASS DDS — WDBE WAITE : Initial value : 0 0 1 1 1 1 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W WAIT Pin Enable 0 Wait input by WAIT pin disabled 1 Wait input by WAIT pin enabled Write Data Buffer Enable 0 Write data buffer function not used 1 Write data buffer function used Reserved Only 1 should be written to this bit DACK Timing Select 0 When DMAC single address trans
PAGE 904
MCR—Memory Control Register Bit H'FED6 Bus Controller 7 6 5 4 3 2 1 0 TPC BE RCDM CW2 MXC1 MXC0 RLW1 RLW0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Refresh Cycle Wait Control 0 1 0 No wait state inserted 1 1 wait state inserted 0 2 wait states inserted 1 3 wait states inserted Multiplex Shift Count 0 1 0 8-bit shift 1 9-bit shift 0 10-bit shift 1 — 2-CAS Method Select 0 16-bit DRAM space selected 1 8-bit DRAM s
PAGE 905
DRAMCR—DRAM Control Register Bit : H'FED7 Bus Controller 7 6 5 4 3 2 1 0 RFSHE RCW RMODE CMF CMIE CKS2 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Refresh Counter Clock Select 0 0 1 1 0 1 0 Count operation disabled 1 Count uses ø/2 0 Count uses ø/8 1 Count uses ø/32 0 Count uses ø/128 1 Count uses ø/512 0 Count uses ø/2048 1 Count uses ø/4096 Compare Match Interrupt Enable 0 Interrupt request (CMI) by CMF
PAGE 906
RTCOR—Refresh Time Constant Register Bit H'FED9 Bus Controller : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the period for compare match operations with RTCNT RAMER—RAM Emulation Register Bit : H'FEDB Bus Controller [for H8S/2398F-ZTAT Only] 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W RAM Select, Flash Memory Area Se
PAGE 907
RAMER—RAM Emulation Register Bit : H'FEDB Bus Controller (for H8S/2357F-ZTAT only) 7 6 5 4 3 2 1 0 — — — — — RAMS RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — — R/W R/W R/W RAM Select, Flash Memory Area RAMS RAM1 RAM0 Area 0 × × H'FFDC00 to H'FFDFFF 1 0 0 H'000000 to H'0003FF 1 H'000400 to H'0007FF 0 H'000800 to H'000BFF 1 H'000C00 to H'000FFF 1 ×: Don’t care MAR0AH—Memory Address Register 0AH MAR0AL—Memory Address Register 0AL H'FE
PAGE 908
ETCR0A—Transfer Count Register 0A Bit : ETCR0A : Initial value : H'FEE6 DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Transfer counter Transfer number storage register Transfer counter Block size storage register Block size counter Block transfer mode * : Undefined MAR0BH—Memory Address Register 0BH MAR0BL—M
PAGE 909
ETCR0B—Transfer Count Register 0B Bit : ETCR0B : Initial value : H'FEEE DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode and idle mode Transfer counter Repeat mode Transfer number storage register Block transfer mode Transfer counter Block transfer counter * : Undefined Note: Not used in normal mode.
PAGE 910
ETCR1A—Transfer Count Register 1A Bit : ETCR1A : Initial value : H'FEF6 DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Transfer counter Repeat mode Transfer number storage register Transfer counter Block size storage register Block size counter Block transfer mode * : Undefined MAR1BH — Memory Address Register 1BH MAR1BL
PAGE 911
IOAR1B—I/O Address Register 1B Bit : IOAR1B : Initial value : H'FEFC DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR1B—Transfer Count Register 1B Bit : ETCR1B : Initial value : Read/Write : H'FEFE DMAC 15 14 13 12 11 10 9 8 7
PAGE 912
DMAWER—DMA Write Enable Register H'FF00 DMAC : 7 6 5 4 3 2 1 0 DMAWER : — — — — WE1B WE1A WE0B WE0A Bit Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Write Enable 0A 0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled 1 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Write Enable 0B 0 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled 1 Writes to a
PAGE 913
DMATCR—DMA Terminal Control Register H'FF01 DMAC Bit : 7 6 5 4 3 2 1 0 DMATCR : — — TEE1 TEE0 — — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — R/W R/W — — — — Transfer End Enable 0 0 TEND0 pin output disabled 1 TEND0 pin output enabled Transfer End Enable 1 DMACR0A—DMA Control Register 0A DMACR0B—DMA Control Register 0B DMACR1A—DMA Control Register 1A DMACR1B—DMA Control Register 1B 0 TEND1 pin output disabled 1 TEND1 pin output enabled H'FF02 H'FF0
PAGE 914
Full address mode (cont) Bit : 7 6 5 4 3 2 1 0 DMACRB : — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Reserved Only 0 should be written to this bit. Reserved Only 0 should be written to this bit.
PAGE 915
Short address mode Bit : 7 6 5 4 3 2 1 0 DMACR : DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Data Transfer Factor Channel A Data Transfer Direction 0 1 0 0 Dual address mode: Transfer with MAR as source address and IOAR as destination address Single address mode: Transfer with MAR as source address and DACK pin as write strobe 1 Dual address mode: Transfer with IOAR as source address and MAR
PAGE 916
DMABCRH — DMA Band Control Register DMABCRL — DMA Band Control Register H'FF06 H'FF07 DMAC DMAC Full address mode Bit : DMABCRH : 15 14 13 12 11 10 9 8 FAE1 FAE0 — — DTA1 — DTA0 — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Reserved Only 0 should be written to this bit. Reserved Only 0 should be written to this bit. Reserved Only 0 should be written to this bit.
PAGE 917
Full address mode (cont) Bit : DMABCRL : 7 6 5 4 DTME1 DTE1 DTME0 DTE0 3 2 0 1 DTIE1B DTIE1A DTIE0B DTIE0A Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Channel 0 Data Transfer Interrupt Enable A 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Channel 0 Data Transfer Interrupt Enable B 0 Transfer suspended interrupt disabled 1 Transfer suspended interrupt enabled Channel 1 Data Transfer Interrupt Enable A 0 Transfer
PAGE 918
Short address mode Bit : DMABCRH : 15 14 13 12 11 10 9 8 FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Channel 0A Data Transfer Acknowledge 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0B Data Transfer Acknowledge 0 Clearing of selected internal interrupt source
PAGE 919
Short address mode (cont) Bit : DMABCRL : 7 6 5 4 DTE1B DTE1A DTE0B DTE0A 3 2 DTIE1B DTIE1A 0 1 DTIE0B DTIE0A Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Channel 0A Data Transfer Interrupt Enable 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Channel 0B Data Transfer Interrupt Enable 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Channel 1A Data Transfer Interrupt Enable 0 Transfer end interru
PAGE 920
ISCRH — IRQ Sense Control Register H ISCRL — IRQ Sense Control Register L H'FF2C H'FF2D Interrupt Controller Interrupt Controller ISCRH Bit : 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 1 0 IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 6 5 4 3 2 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : 0 0 0 0 0 0 0 0 Read/W
PAGE 921
ISR—IRQ Status Register H'FF2F Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit : Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing.
PAGE 922
DTVECR—DTC Vector Register Bit : 7 H'FF37 6 5 4 DTC 3 2 0 1 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/W R/W R/W R/W R/W R/W R/W Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 DTC software activation is enabled [Holding conditions] • When the DIS
PAGE 923
SBYCR—Standby Control Register Bit : H'FF38 Power-Down State 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — — Initial value : 0 0 0 0 1 0 0 0 Read/Write : R/W R/W R/W R/W R/W — — R/W Reserved Only 0 should be written to this bit Output Port Enable 0 In software standby mode, address bus and bus control signals are high-impedance 1 In software standby mode, address bus and bus control signals retain output state Standby Timer Select 0 0 1 1 0 1 0 Standby time = 8
PAGE 924
SYSCR—System Control Register Bit : H'FF39 MCU 7 6 5 4 3 2 1 0 RAME — — INTM1 INTM0 NMIEG — — Initial value : 0 0 0 0 0 0 0 1 Read/Write : R/W — R/W R/W R/W —/(R/W) R/W R/W RAM Enable 0 On-chip RAM disabled 1 On-chip RAM enabled Reserved Only 0 should be written to this bit Reserved for H8S/2398, H8S/2394, H8S/2392, and H8S/2390. Only 0 should be written to this bit.
PAGE 925
SCKCR—System Clock Control Register Bit : H'FF3A Clock Pulse Generator 7 6 5 4 3 2 1 0 PSTOP — — — — SCK2 SCK1 SCK0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W —/(R/W) — — R/W R/W R/W Bus Master Clock Select Reserved for H8S/2398, H8S/2394, H8S/2392, and H8S/2390. Only 0 should be written to this bit. 0 0 1 1 Reserved Only 0 should be written to this bit.
PAGE 926
SYSCR2—System Control Register 2 H'FF42 MCU [F-ZTAT version Only] Bit : 7 6 5 4 3 2 1 0 — — — — FLSHE — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — R/W — — — Flash memory control register enable 0 Flash memory control register is not selected 1 Flash memory control register is selected Note: SYSCR2 can only be accessed in the F-ZTAT version. In other versions, this register cannot be written to and will return an undefined value if read.
PAGE 927
PCR—PPG Output Control Register Bit : 7 H'FF46 6 5 4 PPG 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Output Trigger for Pulse Output Group 0 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 1 0 1 0 Compare match in TPU channel 0 1 Compare match i
PAGE 928
PMR—PPG Output Mode Register Bit : H'FF47 PPG 7 6 5 4 G3INV G2INV G1INV G0INV 3 2 G3NOV G2NOV 1 0 G1NOV G0NOV Initial value : 1 1 1 1 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Pulse Output Group n Normal/Non-Overlap Operation Select 0 Normal operation in pulse output group n (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group n (independent 1 and 0 output at compare match A or B in the sele
PAGE 929
NDERH — Next Data Enable Registers H NDERL — Next Data Enable Registers L H'FF48 H'FF49 PPG PPG NDERH Bit : 7 6 5 4 3 2 1 0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Pulse Output Enable/Disable 0 Pulse outputs PO15 to PO8 are disabled 1 Pulse outputs PO15 to PO8 are enabled NDERL Bit : 7 6 5 4 3 2 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 Initial value : 0 0 0 0 0
PAGE 930
PODRH — Output Data Register H PODRL — Output Data Register L H'FF4A H'FF4B PPG PPG PODRH Bit : 7 6 5 4 3 2 1 0 POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Stores output data for use in pulse output PODRL Bit : 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W
PAGE 931
NDRH—Next Data Register H H'FF4C (FF4E) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4C Bit : 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores the next data for pulse output groups 3 and 2 (b) Address: H'FF4E Bit : 7 6 5 4 3 2 1 0 — — — — — — — — Initial value : 1 1 1 1 1 1 1 1 Read/Write : — — — — — — —
PAGE 932
NDRL—Next Data Register L H'FF4D (FF4F) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores the next data for pulse output groups 1 and 0 (b) Address: H'FF4F Bit : 7 6 5 4 3 2 1 0 — — — — — — — — Initial value : 1 1 1 1 1 1 1 1 Read/Write : — — — — — — — — (
PAGE 933
PORT1—Port 1 Register Bit : H'FF50 Port 1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port 1 pins Note: * Determined by the state of pins P17 to P10.
PAGE 934
PORT5—Port 5 Register Bit : H'FF54 Port 5 7 6 5 4 3 2 1 0 — — — — P53 P52 P51 P50 —* —* —* —* R R R R Initial value : Undefined Undefined Undefined Undefined Read/Write : — — — — State of port 5 pins Note: * Determined by the state of pins P53 to P50.
PAGE 935
PORTC—Port C Register Bit : H'FF5B Port C [On-chip ROM version Only)] 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port C pins Note: * Determined by the state of pins PC7 to PC0.
PAGE 936
PORTG—Port G Register Bit H'FF5F : 7 6 5 4 3 2 1 0 — — — PG4 PG3 PG2 PG1 PG0 —* —* —* —* —* R R R R R Initial value : Undefined Undefined Undefined Read/Write : Port G — — — State of port G pins Note: * Determined by the state of pins PG4 to PG0.
PAGE 937
P5DR—Port 5 Data Register Bit H'FF64 : Port 5 7 6 5 4 3 2 1 0 — — — — P53DR P52DR P51DR P50DR 0 0 0 0 R/W R/W R/W R/W Initial value : Undefined Undefined Undefined Undefined Read/Write : — — — — Stores output data for port 5 pins (P53 to P50) P6DR—Port 6 Data Register Bit H'FF65 : Port 6 7 6 5 4 3 2 1 0 P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores out
PAGE 938
PCDR—Port C Data Register Bit : H'FF6B Port C 7 6 5 4 3 2 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 1 0 PC1DR PC0DR Stores output data for port C pins (PC7 to PC0) PDDR—Port D Data Register Bit : H'FF6C Port D 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output
PAGE 939
PGDR—Port G Data Register Bit : H'FF6F 7 6 5 — — — 4 — — 3 2 PG4DR PG3DR PG2DR Initial value : Undefined Undefined Undefined Read/Write : Port G — 0 1 PG1DR PG0DR 0 0 0 0 0 R/W R/W R/W R/W R/W Stores output data for port G pins (PG4 to PG0) PAPCR—Port A MOS Pull-Up Control Register Bit : 7 6 H'FF70 5 4 Port A [On-chip ROM version Only] 3 2 0 1 PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/
PAGE 940
PDPCR—Port D MOS Pull-Up Control Register Bit : 7 6 H'FF73 5 Port D [On-chip ROM version Only] 4 3 2 0 1 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PAGE 941
SMR0—Serial Mode Register 0 Bit : H'FF78 SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 ø clock 1 ø/4 clock 0 ø/16 clock 1 ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Parity bit addition and chec
PAGE 942
SMR0—Serial Mode Register 0 Bit : H'FF78 Smart Card Interface 0 7 6 5 4 3 2 1 0 GM CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 ø clock 1 ø/4 clock 0 ø/16 clock 1 ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Setting prohibited Stop Bit Length 0 Setting prohibited 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Setting prohibi
PAGE 943
BRR0—Bit Rate Register 0 Bit H'FF79 SCI0, Smart Card Interface 0 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.
PAGE 944
SCR0—Serial Control Register 0 Bit : H'FF7A SCI0 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 0 1 1 0 1 Asynchronous mode Internal clock/SCK pin functions as I/O port Synchronous mode Asynchronous mode Synchronous mode Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial
PAGE 945
SCR0—Serial Control Register 0 Bit : H'FF7A Smart Card Interface 0 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable SCMR SMR SCR setting SMIF C/A,GM CKE1 0 CKE0 SCK pin function See SCI specification 1 0 0 0 Operates as port input pin 1 0 0 1 Clock output as SCK output pin 1 1 0 0 Fixed-low output as SCK output pin 1 1 0 1 Clock output as SCK output pin
PAGE 946
SSR0—Serial Status Register 0 Bit : H'FF7C SCI0 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit
PAGE 947
SSR0—Serial Status Register 0 Bit : H'FF7C Smart Card Interface 0 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1
PAGE 948
RDR0—Receive Data Register 0 Bit : H'FF7D 7 6 5 SCI0, Smart Card Interface 0 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR0—Smart Card Mode Register 0 Bit : H'FF7E SCI0, Smart Card Interface 0 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart Card Interface Mode Select 0 Smart Card interface function is disabled 1 Sma
PAGE 949
SMR1—Serial Mode Register 1 Bit : H'FF80 SCI1 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 ø clock 1 ø/4 clock 0 ø/16 clock 1 ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Parity bit addition and chec
PAGE 950
SMR1—Serial Mode Register 1 Bit : H'FF80 Smart Card Interface 1 7 6 5 4 3 2 1 0 GM CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 ø clock 1 ø/4 clock 0 ø/16 clock 1 ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Setting prohibited Stop Bit Length 0 Setting prohibited 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Setting prohibi
PAGE 951
BRR1—Bit Rate Register 1 Bit H'FF81 SCI1, Smart Card Interface 1 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.
PAGE 952
SCR1—Serial Control Register 1 Bit : H'FF82 SCI1 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 1 0 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output 1 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as clock output*1 0 Asynchronous mode Synchronous mode 1 Async
PAGE 953
SCR1—Serial Control Register 1 Bit : H'FF82 Smart Card Interface 1 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable SCMR SMR SCR setting SMIF C/A,GM CKE1 0 CKE0 SCK pin function See SCI specification 1 0 0 0 Operates as port input pin 1 0 0 1 Clock output as SCK output pin 1 1 0 0 Fixed-low output as SCK output pin 1 1 0 1 Clock output as SCK output pin
PAGE 954
SSR1—Serial Status Register 1 Bit : H'FF84 SCI1 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit
PAGE 955
SSR1—Serial Status Register 1 Bit : H'FF84 Smart Card Interface 1 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1
PAGE 956
RDR1—Receive Data Register 1 Bit H'FF85 SCI1, Smart Card Interface 1 : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR1—Smart Card Mode Register 1 Bit : H'FF86 SCI1, Smart Card Interface 1 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart Card Interface Mode Select 0 Smart Card interface function is disabled 1 Sm
PAGE 957
SMR2—Serial Mode Register 2 Bit : H'FF88 SCI2 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 ø clock 1 ø/4 clock 0 ø/16 clock 1 ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Parity bit addition and chec
PAGE 958
SMR2—Serial Mode Register 2 Bit : H'FF88 Smart Card Interface 2 7 6 5 4 3 2 1 0 GM CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 ø clock 1 ø/4 clock 0 ø/16 clock 1 ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Setting prohibited Stop Bit Length 0 Setting prohibited 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Setting prohibi
PAGE 959
BRR2—Bit Rate Register 2 Bit H'FF89 SCI2, Smart Card Interface 2 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.
PAGE 960
SCR2—Serial Control Register 2 Bit : H'FF8A SCI2 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 1 0 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output 1 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as clock output*1 0 Asynchronous mode Synchronous mode 1 Async
PAGE 961
SCR2—Serial Control Register 2 Bit : H'FF8A Smart Card Interface 2 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable SCMR SMR SCR setting SMIF C/A,GM CKE1 0 SCK pin function CKE0 See SCI specification 1 0 0 0 Operates as port input pin 1 0 0 1 Clock output as SCK output pin 1 1 0 0 Fixed-low output as SCK output pin 1 1 0 1 Clock output as SCK output pin
PAGE 962
SSR2—Serial Status Register 2 Bit : H'FF8C SCI2 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit
PAGE 963
SSR2—Serial Status Register 2 Bit : H'FF8C Smart Card Interface 2 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1
PAGE 964
RDR2—Receive Data Register 2 Bit H'FF8D SCI2, Smart Card Interface 2 : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR2—Smart Card Mode Register 2 Bit : H'FF8E SCI2, Smart Card Interface 2 7 6 5 4 3 2 1 0 SMIF — — — — SDIR SINV — Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart Card Interface Mode Select 0 Smart Card interface function is disabled 1 Smart
PAGE 965
ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL — — — — — — — — Bit A/D Data Register AH A/D Data Register AL A/D Data Register BH A/D Data Register BL A/D Data Register CH A/D Data Register CL A/D Data Register DH A/D Data Register DL : 15 14 13 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 12 11 10 9 A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 A
PAGE 966
ADCSR—A/D Control/Status Register Bit : H'FF98 A/D Converter 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/W R/W R/W R/W R/W R/W R/W Channel Select Channel select Group select Single Mode Group Mode CH2 CH1 CH0 0 0 0 AN0 AN0 1 0 1 0 1 0 1 AN1 AN0, AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 1 1 0 1 Group Select 0 Conversion time= 266 states (max.
PAGE 967
ADCR—A/D Control Register Bit : H'FF99 A/D 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — — — — — 1 1 Initial value : 0 0 1 1 Read/Write : R/W R/W — — —/(R/W)* —/(R/W)* 1 1 — — Timer Trigger Select Description TRGS1 TRGS1 0 1 0 A/D conversion start by external trigger is disabled 1 A/D conversion start by external trigger (TPU) is enabled 0 A/D conversion start by external trigger (8-bit timer) is enabled 1 A/D conversion start by external trigger pin (ADTRG) is enabled Note
PAGE 968
DACR—D/A Control Register Bit H'FFA6 : D/A 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value : 0 0 0 1 1 1 1 1 Read/Write : R/W R/W R/W — — — — — D/A Output Enable 0 0 Analog output DA0 is disabled 1 Channel 0 D/A conversion is enabled Analog output DA0 is enabled D/A Output Enable 1 0 Analog output DA1 is disabled 1 Channel 1 D/A conversion is enabled Analog output DA1 is enabled D/A Conversion Control DAOE1 DAOE0 DAE Description 0 0 × Channel 0 an
PAGE 969
TCR0—Time Control Register 0 TCR1—Time Control Register 1 Bit : H'FFB0 H'FFB1 8-Bit Timer Channel 0 8-Bit Timer Channel 1 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 1 1 0 1 0 Clock input disabled 1 Internal clock: counted at falling edge of ø/8 0 Internal clock: counted at falling edge of ø/64 1 Internal clock: counted at falling edge of ø/8192 0
PAGE 970
TCSR0—Timer Control/Status Register 0 TCSR1—Timer Control/Status Register 1 TCSR0 Bit : H'FFB2 H'FFB3 8-Bit Timer Channel 0 8-Bit Timer Channel 1 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W TCSR1 Bit : Initial value : Read/Write : 7 6 5 4 3 2 1 0 CMFB CMFA OVF — OS3 OS2 OS1 OS0 0 0 0 1 0 0 0 0 R/(W)* R/(W)* R/(W)* — R/W R/W R/W R/W Output Selec
PAGE 971
TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 H'FFB4 H'FFB5 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORA0 Bit TCORA1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 H'FFB6 H'FFB7 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORB0 Bit TCORB1 : 15 14 13 12
PAGE 972
TCSR—Timer Control/Status Register Bit : H'FFBC (W), H'FFBC (R) WDT 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 Initial value : 0 0 0 1 1 0 0 0 Read/Write : R/(W)* R/W R/W — — R/W R/W R/W Clock Select CKS2 CKS1 CKS0 0 0 1 1 0 1 Clock Overflow period* (when ø = 20 MHz) 0 ø/2 (initial value) 25.6µs 1 ø/64 819.2µs 0 ø/128 1.6ms 1 ø/512 6.6ms 0 ø/2,048 26.2ms 1 ø/8,192 104.9ms 0 ø/32,768 419.4ms 1 ø/131,072 1.
PAGE 973
TCNT—Timer Counter H'FFBC (W), H'FFBD (R) WDT : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit TCNT is an 8-bit readable/writable* up-counter. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access.
PAGE 974
TSTR—Timer Start Register Bit : H'FFC0 TPU 7 6 5 4 3 2 1 0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Counter Start 0 TCNTn count operation is stopped 1 TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained.
PAGE 975
FLMCR1—Flash Memory Control Register 1 Bit : H'FFC8 FLASH (For the H8S/2357 F-ZTAT) 7 6 5 4 3 2 1 0 FWE SWE — — EV PV E P Initial value : —* 0 0 0 0 0 0 0 Read/Write : R R/W — — R/W R/W R/W R/W Program 0 Clears program mode 1 Program mode is entered [Setting condition] FWE=1, SWE=1, and PSU=1 Erase 0 Clears erase mode 1 Erase mode is entered [Setting condition] FWE=1, SWE=1, and ESU=1 Program Verify 0 Clears program verify mode 1 Program verify mode is enter
PAGE 976
FLMCR2—Flash Memory Control Register 2 Bit : H'FFC9 FLASH (For the H8S/2357 F-ZTAT) 7 6 5 4 3 2 1 0 FLER — — — — — ESU PSU 0 0 0 R/W R/W Initial value : 0 0 0 0 0 Read/Write : R — — — — — Program Setup 0 Clears program setup 1 Program setup [Setting condition] FWE=1 and SWE=1 Erase Setup 0 Clears erase setup 1 Erase setup [Setting condition] FWE=1 and SWE=1 Flash Memory Error 0 Flash memory operates normally.
PAGE 977
EBR1—Erase Block Specification Register 1 H'FFCA EBR2— Erase Block Specification Register 2 H'FFCB Bit : EBR1 FLASH (For the H8S/2357 F-ZTAT) FLASH (For the H8S/2357 F-ZTAT) 7 6 5 4 3 2 1 0 — — — — — — EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — — — R/W R/W Bit : EBR2 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Deviding Erase Blocks
PAGE 978
FLMCR1—Flash Memory Control Register 1 Bit : H'FFC8 FLASH (For the H8S/2398 F-ZTAT) 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P Initial value : 1 0 0 0 0 0 0 0 Read/Write : R R/W R/W R/W R/W R/W R/W R/W Program 1* 0 Clears program mode 1 Program mode is entered [Setting condition] SWE=1 and PSU=1 Erase 1* 0 Clears erase mode 1 Erase mode is entered [Setting condition] SWE=1 and ESU=1 Program Verify 1* 0 Clears program verify mode 1 Program verify mode is enter
PAGE 979
FLMCR2—Flash Memory Control Register 2 Bit : H'FFC9 FLASH (For the H8S/2398 F-ZTAT) 7 6 5 4 3 2 1 0 FLER — — — — — — — 0 0 0 — — Initial value : 0 0 0 0 0 Read/Write : R — — — — — Flash Memory Error 0 Flash memory operates normally. Writing/erasing protect (error protect) to flash memory is disabled. [Clearing condition] Reset or hardware standby mode 1 Indicates that an error occurs in writing/erasing to flash memory.
PAGE 980
TCR0—Timer Control Register 0 Bit : H'FFD0 7 6 5 CCLR2 CCLR1 CCLR0 4 TPU0 3 CKEG1 CKEG0 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on ø/1 1 Internal clock: counts on ø/4 0 Internal clock: counts on ø/16 1 Internal clock: counts on ø/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: count
PAGE 981
TMDR0—Timer Mode Register 0 Bit : H'FFD1 TPU0 7 6 5 4 3 2 1 0 — — BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — × : Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2.
PAGE 982
TIOR0H—Timer I/O Control Register 0H Bit : H'FFD2 TPU0 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR0A I/O Control 0 0 0 1 1 0 1 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 0 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 1 0 0 0 0 1 1 0 0 1 Toggle outp
PAGE 983
TIOR0L—Timer I/O Control Register 0L Bit H'FFD3 TPU0 : 7 6 5 4 3 2 1 0 : IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR0C I/O Control 0 0 0 0 1 1 0 TGR0C Output disabled is output compare Initial output is register 0 output 1 1 0 1 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 0 1 1 0 output at co
PAGE 984
TIER0—Timer Interrupt Enable Register 0 Bit : H'FFD4 TPU0 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — — R/W R/W R/W R/W R/W TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 Interrupt requ
PAGE 985
TSR0—Timer Status Register 0 Bit : Initial value : Read/Write : H'FFD5 TPU0 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA 1 1 0 0 0 0 0 0 — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] •
PAGE 986
TCNT0—Timer Counter 0 Bit H'FFD6 TPU0 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A—Timer General Register 0A TGR0B—Timer General Register 0B TGR0C—Timer General Register 0C TGR0D—Timer General Register 0D Bit H'FFD8 H'FFDA H'FFDC H'FFDE TPU0 TPU0 TPU0 TPU0 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1
PAGE 987
TCR1—Timer Control Register 1 Bit : H'FFE0 7 6 5 — CCLR1 CCLR0 4 TPU1 3 CKEG1 CKEG0 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on ø/1 1 Internal clock: counts on ø/4 0 Internal clock: counts on ø/16 1 Internal clock: counts on ø/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on ø
PAGE 988
TMDR1—Timer Mode Register 1 Bit : H'FFE1 TPU1 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — × : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Oct.28.
PAGE 989
TIOR1—Timer I/O Control Register 1 Bit : H'FFE2 TPU1 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR1A I/O Control 0 0 0 0 1 1 0 TGR1A Output disabled is output compare Initial output is register 0 output 1 1 0 1 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 × × × 1 output at compare match Toggle output at compare match 0 1 1 0 output at compare
PAGE 990
TIER1—Timer Interrupt Enable Register 1 Bit : H'FFE4 TPU1 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 Interrupt requests (T
PAGE 991
TSR1—Timer Status Register 1 Bit : H'FFE5 TPU1 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : Read/Write : 1 1 0 0 0 0 0 0 R — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When
PAGE 992
TGR1A—Timer General Register 1A TGR1B—Timer General Register 1B Bit H'FFE8 H'FFEA TPU1 TPU1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCR2—Timer Control Register 2 Bit : H'FFF0 7 6 5 — CCLR1 CCLR0 Initial value : 0 0 0 0 Read/Write : — R/W R/W R/W 4 TPU2 3 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 0 R/W R/W R/W R/W CKEG1 CKEG0
PAGE 993
TMDR2—Timer Mode Register 2 Bit : H'FFF1 TPU2 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 × × 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — × : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Oct.28.
PAGE 994
TIOR2—Timer I/O Control Register 2 Bit : H'FFF2 TPU2 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR2A I/O Control 0 0 0 1 0 TGR2A is output 1 compare 0 register Output disabled Initial output is 0 output 1 1 0 1 Output disabled 1 Initial output is 1 output 1 1 × 0 1 0 TGR2A is input 1 capture × register 1 output at compare match Toggle output at compare match 0 0
PAGE 995
TIER2—Timer Interrupt Enable Register 2 Bit : H'FFF4 TPU2 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 Interrupt requests
PAGE 996
TSR2—Timer Status Register 2 Bit : H'FFF5 TPU2 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • Whe
PAGE 997
TCNT2—Timer Counter 2 Bit H'FFF6 TPU2 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
PAGE 998
Appendix C I/O Port Block Diagrams C.
PAGE 999
R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C P1n WDR1 RDR1 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input External clock input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 2, 3, 5, 7 Figure C-1 (b) Port 1 Block Diagram (Pins P12, P13, P15, and P17) Rev.6.00 Oct.28.
PAGE 1000
R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C P1n WDR1 RDR1 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 4 or 6 Figure C-1 (c) Port 1 Block Diagram (Pins P14 and P16) Rev.6.00 Oct.28.
PAGE 1001
Port 2 Block Diagram Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n WDR2 RDR2 Internal data bus C.2 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR2 Input capture input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 n = 0 or 1 Figure C-2 (a) Port 2 Block Diagram (Pins P20 and P21) Rev.6.00 Oct.28.
PAGE 1002
R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n WDR2 RDR2 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR2 Input capture input 8-bit timer module Counter external reset input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 n = 2 or 4 Figure C-2 (b) Port 2 Block Diagram (Pins P22 and P24) Rev.6.00 Oct.28.
PAGE 1003
R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n WDR2 RDR2 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR2 Input capture input 8-bit timer module Counter external reset input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 n = 3 or 5 Figure C-2 (c) Port 2 Block Diagram (Pins P23 and P25) Rev.6.00 Oct.28.
PAGE 1004
R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n WDR2 Internal data bus Reset PPG module Pulse output enable Pulse output 8-bit timer Compare-match output enable Compare-match output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 n = 6 or 7 Figure C-2 (d) Port 2 Block Diagram (Pins P26 and P27) Rev.6.00 Oct.28.
PAGE 1005
Port 3 Block Diagram Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C P3n Internal data bus C.3 WDR3 Reset *2 R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: n = 0 or 1 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C-3 (a) Port 3 Block Diagram (Pins P30 and P31) Rev.6.00 Oct.28.
PAGE 1006
R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C P3n Internal data bus Reset WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial receive data enable RDR3 RPOR3 Serial receive data Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: n = 2 or 3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C-3 (b) Port 3 Block Diagram (Pins P32 and P33) Rev.6.00 Oct.28.
PAGE 1007
Reset Internal data bus R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C P3n WDR3 Reset *2 R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output Serial clock input enable RDR3 RPOR3 Legend: Serial clock input WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RDR3: Read P3DR RPOR3: Read port 3 RODR3: Read P3ODR n = 4 or 5 Notes: 1. Output enable signal 2. Open drain control signal Figure C-3 (c) Port 3 Block Diagram (Pins P34 and P35) Rev.6.00 Oct.28.
PAGE 1008
Port 4 Block Diagram RPOR4 P4n Internal data bus C.4 A/D converter module Analog input Legend: RPOR4 : Read port 4 n = 0 to 5 RPOR4 P4n Internal data bus Figure C-4 (a) Port 4 Block Diagram (Pins P40 to P45) A/D converter module Analog input D/A converter module Output enable Analog output Legend: RPOR4 : Read port 4 n = 6 or 7 Figure C-4 (b) Port 4 Block Diagram (Pins P46 and P47) Rev.6.00 Oct.28.
PAGE 1009
Port 5 Block Diagram Reset R Q D P50DDR C Internal data bus C.5 WDDR0 Reset R Q D P50DR C P50 WDR5 SCI module Serial transmit data output enable Serial transmit data RDR5 RPOR5 Legend: WDDR5: WDR5: RDR5: RPOR5: Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C-5 (a) Port 5 Block Diagram (Pin P50) Rev.6.00 Oct.28.
PAGE 1010
R Q D P51DDR C WDDR5 Reset R Q D P51DR C P51 WDR5 Internal data bus Reset SCI module Serial receive data enable RDR5 RPOR5 Serial receive data Legend: WDDR5: Write to P5DDR WDR5: Write to P5DR RDR5: Read P5DR RPOR5: Read port 5 Figure C-5 (b) Port 5 Block Diagram (Pin P51) Rev.6.00 Oct.28.
PAGE 1011
Reset Internal data bus R Q D P52DDR C WDDR5 Reset R Q D P52DR C P52 WDR5 SCI module Serial clock output enable Serial clock output Serial clock input enable RDR5 RPOR5 Serial clock input Legend: WDDR5: WDR5: RDR5: RPOR5: Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C-5 (c) Port 5 Block Diagram (Pin P52) Rev.6.00 Oct.28.
PAGE 1012
R Q D P53DDR C WDDR5 Reset R Q D P53DR C P53 Internal data bus Reset WDR5 RDR5 RPOR5 A/D converter A/D converter external trigger input Legend: WDDR5: WDR5: RDR5: RPOR5: Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C-5 (d) Port 5 Block Diagram (Pin P53) Rev.6.00 Oct.28.
PAGE 1013
Port 6 Block Diagram Reset R Q D P60DDR C Internal data bus C.6 WDDR6 Mode 7 P60 Mode 4/5/6 Reset R Q D P60DR C WDR6 Bus controller Chip select RDR6 RPOR6 DMA controller DMA request input Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Figure C-6 (a) Port 6 Block Diagram (Pin P60) Rev.6.00 Oct.28.
PAGE 1014
R Q D P61DDR C WDDR6 Mode 7 P61 Mode 4/5/6 Reset R Q D P61DR C WDR6 Internal data bus Reset Bus controller Chip select DMA controller DMA transfer end enable DMA transfer end RDR6 RPOR6 Legend: WDDR6: Write to P6DDR WDR6: Write to P6DR RDR6: Read P6DR RPOR6: Read port 6 Figure C-6 (b) Port 6 Block Diagram (Pin P61) Rev.6.00 Oct.28.
PAGE 1015
Reset Internal data bus R Q D P62DDR C WDDR6 Reset R Q D P62DR C P62 WDR6 RDR6 RPOR6 DMA controller DMA request input Legend: WDDR6: Write to P6DDR WDR6: Write to P6DR RDR6: Read P6DR RPOR6: Read port 6 Figure C-6 (c) Port 6 Block Diagram (Pin P62) Rev.6.00 Oct.28.
PAGE 1016
R Q D P63DDR C WDDR6 Reset R Q D P63DR C P63 Internal data bus Reset WDR6 DMA controller DMA transfer end enable DMA transfer end RDR6 RPOR6 Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Figure C-6 (d) Port 6 Block Diagram (Pin P63) Rev.6.00 Oct.28.
PAGE 1017
Reset Internal data bus R Q D P6nDDR C WDDR6 Reset R Q D P6nDR C P6n WDR6 RDR6 RPOR6 Interrupt controller IRQ interrupt input Legend: WDDR6: Write to P6DDR WDR6: Write to P6DR RDR6: Read P6DR RPOR6: Read port 6 n = 4 or 5 Figure C-6 (e) Port 6 Block Diagram (Pins P64 and P65) Rev.6.00 Oct.28.
PAGE 1018
R Q D P6nDDR C WDDR6 Mode 7 P6n Mode 4/5/6 Reset R Q D P6nDR C WDR6 Internal data bus Reset Bus controller Chip select RDR6 RPOR6 Interrupt controller IRQ interrupt input Legend: WDDR6: Write to P6DDR WDR6: Write to P6DR RDR6: Read P6DR RPOR6: Read port 6 n = 6 or 7 Figure C-6 (f) Port 6 Block Diagram (Pins P66 and P67) Rev.6.00 Oct.28.
PAGE 1019
Port A Block Diagram R Q D PAnPCR C WPCRA RPCRA Mode 4/5 Internal address bus Reset Internal data bus C.7 Reset R Q D PAnDDR C WDDRA *1 Reset Mode 7 Mode 4/5/6 PAn R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA RDRA RPORA Legend: WDDRA: Write to PADDR WDRA: Write to PADR WODRA: Write to PAODR WPCRA: Write to PAPCR RDRA: Read PADR RPORA: Read port A RODRA: Read PAODR RPCRA: Read PAPCR n = 0 to 3 Notes: 1. Output enable signal 2.
PAGE 1020
WPCRA RPCRA Mode 4/5 Internal address bus R Q D PA4PCR C Internal data bus Reset Reset R Q D PA4DDR C WDDRA *1 Reset Mode 7 Mode 4/5/6 PA4 R Q D PA4DR C WDRA Reset *2 R Q D PA4ODR C WODRA RODRA RDRA RPORA Interrupt controller Legend: WDDRA: Write to PADDR WDRA: Write to PADR WODRA: Write to PAODR WPCRA: Write to PAPCR RDRA: Read PADR RPORA: Read port A RODRA: Read PAODR RPCRA: Read PAPCR IRQ interrupt input Notes: 1. Output enable signal 2.
PAGE 1021
WPCRA RPCRA Internal address bus R Q D PAnPCR C Internal data bus Reset Reset R Q D PAnDDR C WDDRA *1 Reset Mode 7 Mode 4/5/6 PAn R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA RDRA RPORA Interrupt controller Legend: WDDRA: Write to PADDR WDRA: Write to PADR WODRA: Write to PAODR WPCRA: Write to PAPCR RDRA: Read PADR RPORA: Read port A RODRA: Read PAODR RPCRA: Read PAPCR n = 5 to 7 IRQ interrupt input Notes: 1. Output enable signal 2.
PAGE 1022
C.8 Port B Block Diagram WPCRB RPCRB Mode 4/5 Reset R Q D PBnDDR C WDDRB Reset Mode 7 Mode 4/5/6 PBn R Q D PBnDR C WDRB RDRB RPORB Legend: WDDRB: Write to PBDDR WDRB: Write to PBDR WPCRB: Write to PBPCR RDRB: Read PBDR RPORB: Read port B RPCRB: Read PBPCR n = 0 to 7 Figure C-8 Port B Block Diagram (Pin PB0 to PB7) Rev.6.00 Oct.28.
PAGE 1023
Port C Block Diagram R Q D PCnPCR C WPCRC RPCRC Internal address bus Reset Internal data bus C.9 Mode 4/5 Reset R Q D PCnDDR C WDDRC Reset Mode 7 Mode 4/5/6 PCn R Q D PCnDR C WDRC RDRC RPORC Legend: WDDRC: Write to PCDDR WDRC: Write to PCDR WPCRC: Write to PCPCR RDRC: Read PCDR RPORC: Read port C RPCRC: Read PCPCR n = 0 to 7 Figure C-9 Port C Block Diagram (Pin PC0 to PC 7) Rev.6.00 Oct.28.
PAGE 1024
C.10 Port D Block Diagram WPCRD RPCRD Reset Mode 7 External address write Mode 4/5/6 R Q D PDnDDR C WDDRD Reset R Q D PDnDR C Mode 7 Mode 4/5/6 PDn WDRD External address upper write External address lower write RDRD RPORD Legend: External address upper read WDDRD: Write to PDDDR WDRD: Write to PDDR WPCRD: Write to PDPCR RDRD: Read PDDR RPORD: Read port D RPCRD: Read PDPCR n = 0 to 7 External address lower read Figure C-10 Port D Block Diagram (Pin PD0 to PD 7) Rev.6.00 Oct.28.
PAGE 1025
Port E Block Diagram R Q D PEnPCR C WPCRE RPCRE Internal lower data bus Reset Internal upper data bus C.11 Mode 7 Mode 4/5/6 8-bit bus mode External address write Mode 4/5/6 16-bit bus mode Mode 7 Mode 4/5/6 PEn Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE RDRE RPORE External address lower read Legend: WDDRE: Write to PEDDR WDRE: Write to PEDR WPCRE: Write to PEPCR RDRE: Read PEDR RPORE: Read port E RPCRE: Read PEPCR n = 0 to 7 Figure C-11 Port E Block Diagram (Pin PE0 to PE7) Rev.6.
PAGE 1026
Port F Block Diagram Reset R Q D PF0DDR C Mode 4/5/6 WDDRF Reset Internal data bus C.12 Bus controller BRLE bit R Q D PF0DR C PF0 WDRF RDRF RPORF Bus request input Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Figure C-12 (a) Port F Block Diagram (Pin PF0) Rev.6.00 Oct.28.
PAGE 1027
Reset Internal data bus R Q D PF1DDR C WDDRF Reset R Q D PF1DR C PF1 WDRF Mode 4/5/6 Bus controller BRLE output Bus request acknowledge output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-12 (b) Port F Block Diagram (Pin PF1) Rev.6.00 Oct.28.
PAGE 1028
R Q D PF2DDR C WDDRF Reset Mode 4/5/6 PF2 Mode 4/5/6 Internal data bus Reset Bus controller Wait enable R Q D PF2DR C WDRF Mode 4/5/6 Bus request output enable Bus request output RDRF RPORF Wait input LCAS output enable LCAS output Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Figure C-12 (c) Port F Block Diagram (Pin PF2) Rev.6.00 Oct.28.
PAGE 1029
Mode 4/5/6 R Q D PF3DDR C WDDRF Mode 7 PF3 Mode 4/5/6 Reset R Q D PF3DR C Internal data bus Reset WDRF Bus controller LWR output RDRF RPORF Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Figure C-12 (d) Port F Block Diagram (Pin PF3) Rev.6.00 Oct.28.
PAGE 1030
Mode 4/5/6 R Q D PF4DDR C WDDRF Mode 7 PF4 Mode 4/5/6 Reset R Q D PF4DR C Internal data bus Reset WDRF Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-12 (e) Port F Block Diagram (Pin PF4) Rev.6.00 Oct.28.
PAGE 1031
Mode 4/5/6 R Q D PF5DDR C WDDRF Mode 7 PF5 Mode 4/5/6 Reset R Q D PF5DR C Internal data bus Reset WDRF Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-12 (f) Port F Block Diagram (Pin PF5) Rev.6.00 Oct.28.
PAGE 1032
Mode 4/5/6 R Q D PF6DDR C WDDRF Mode 7 PF6 Mode 4/5/6 Reset R Q D PF6DR C Internal data bus Reset WDRF Bus controller AS output RDRF RPORF Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Figure C-12 (g) Port F Block Diagram (Pin PF6) Rev.6.00 Oct.28.
PAGE 1033
Reset S* R Q D PF7DDR C WDDRF Reset R Q D PF7DR C PF7 Internal data bus Mode 4/5/6 WDRF ø RDRF RPORF Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Note: * Set priority Figure C-12 (h) Port F Block Diagram (Pin PF7) Rev.6.00 Oct.28.
PAGE 1034
C.13 Port G Block Diagram R Q D PG0DDR C WDDRG Reset R Q D PG0DR C PG0 Internal data bus Reset WDRG Mode 4/5/6 Bus controller CAS enable CAS output RDRG RPORG Legend: WDDRG: Write to PGDDR WDRG: Write to PGDR RDRG: Read PGDR RPORG: Read port G Figure C-13 (a) Port G Block Diagram (Pin PG0) Rev.6.00 Oct.28.
PAGE 1035
R Q D PGnDDR C WDDRG Mode 7 PGn Mode 4/5/6 Reset R Q D PGnDR C Internal data bus Reset WDRG Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: n = 1 to 3 Write to PGDDR Write to PGDR Read PGDR Read port G Figure C-13 (b) Port G Block Diagram (Pins PG1 to PG3) Rev.6.00 Oct.28.
PAGE 1036
Mode Mode 4/5 6/7 S R Q D PG4DDR C WDDRG Reset Mode 7 PG4 Mode 4/5/6 R Q D PG4DR C Internal data bus Reset WDRG Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C-13 (c) Port G Block Diagram (Pin PG4) Rev.6.00 Oct.28.
PAGE 1037
Appendix D Pin States D.
PAGE 1038
MCU Port Name Operating Pin Name Mode PowerOn Reset Port B 4, 5 Port C Port D Port E Manual Reset*2 Bus Release State L kept T [OPE = 0] T [OPE = 1] kept T 6 T kept T [DDR · OPE = 0] T T [DDR · OPE = 1] kept [DDR = 0] Input port [DDR = 1] Address output 7 T kept T kept kept I/O port 4, 5 L kept T [OPE = 0] T [OPE = 1] kept T Address output 6 T kept T [DDR · OPE = 0] T T [DDR · OPE = 1] kept [DDR = 0] Input port [DDR = 1] Address output 7 T kept T kept kept I/O p
PAGE 1039
Bus Release State Program Execution State Sleep Mode [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] kept [WAITE = 1] T [LCASE = 1, OPE = 0] T [LCASE = 1, OPE = 1] LCAS [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] T [BREQOE + WAITE + LCASE= 0] I/O port [BREQOE = 1] BREQO [WAITE = 1] WAIT [LCASE = 1] LCAS T kept kept I/O port [BRLE = 0] kept [BRLE = 1] BACK T [BRLE = 0] kept [BRLE = 1] H L [BRLE = 0] I/O port [BRLE = 1] BACK T kept T kept kept I/O port 4 t
PAGE 1040
BREQOE: BREQO pin enable DRAME: DRAM space setting LCASE: DRAM space setting, CW2 = LCASS = 0 Notes: 1. Indicates the state after completion of the executing bus cycle. 2. Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.
PAGE 1041
Appendix E Pin States at Power-On Note that pin states at power-on depend on the state of the STBY pin and NMI pin. The case in which pins settle* from an indeterminate state at power-on, and the case in which pins settle* from the high-impedance state, are described below. After reset release, power-on reset exception handling is started. Note: * “Settle” refers to the pin states in a power-on reset in each MCU operating mode. E.
PAGE 1042
E.2 When Pins Settle from the High-Impedance State at Power-On When the STBY pin level changes from low to high after powering on, the chip goes to the power-on reset state* after a high level is detected at the STBY pin. While the chip detects a low level at the STBY pin, it is in the hardware standby mode. During this interval, the pins are in the high-impedance state. After detecting a high level at the STBY pin, the chip starts oscillation.
PAGE 1043
Appendix F F.1 Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more).
PAGE 1044
Appendix G Product Code Lineup Table G.1 H8S/2357, H8S/2352 Group Product Code Lineup Product Type H8S/2357 Masked ROM ZTAT F-ZTAT H8S/2352 Table G.
PAGE 1045
Appendix H Package Dimensions Figures H-1 and H-2 show the TFP-120 and FP-128B package dimensions of the H8S/2357 Group. As of January, 2003 16.0 ± 0.2 Unit: mm 14 90 61 60 120 31 0.10 1.0 0˚ – 8˚ 0.5 ± 0.1 0.10 ± 0.10 0.07 M 1.2 1.20 Max 30 1.00 1 *0.17 ± 0.05 0.15 ± 0.04 *0.17 ± 0.05 0.15 ± 0.04 0.4 16.0 ± 0.2 91 Package Code JEDEC JEITA Mass (reference value) *Dimension including the plating thickness Base material dimension TFP-120 — Conforms 0.
PAGE 1046
Rev.6.00 Oct.28.
PAGE 1047
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2357 Group, H8S/2357F-ZTATTM,H8S/2398F-ZTATTM Publication Date: 1st Edition, November, 1997 Rev.6.00, October 28, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.  2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
PAGE 1048
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
PAGE 1049
H8S/2357 Group, H8S/2357F-ZTATTM, H8S/2398F-ZTATTM Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0138-0600H