Datasheet

Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 937 of 980
REJ09B0050-0600
Item Symbol Min. Max. Unit Test Conditions
A/D
converter
Trigger input setup time t
TRGS
30 ⎯ ns Figure 25.38
IIC2 SCL input cycle time t
SCL
12 t
cyc
+600 ⎯ ns Figure 25.39
SCL input high pulse width t
SCLH
3 t
cyc
+300 ⎯ ns
SCL input low pulse width t
SCLL
5 t
cyc
+300 ⎯ ns
SCL, SDA Input falling time t
Sf
⎯ 300 ns
SCL, SDA Input spike pulse
removal time
t
SP
⎯ 1 t
cyc
ns
SDA input bus free time t
BUF
5 t
cyc
⎯ ns
Start condition input hold
time
t
STAH
3 t
cyc
⎯ ns
Retransmit start condition
input setup time
t
STAS
3 t
cyc
⎯ ns
Stop condition input setup
time
t
STOS
1 t
cyc
+20 ⎯ ns
Data input setup time t
SDAS
0 ⎯ ns
Data input hold time t
SDAH
0 ⎯ ns
SCL, SDA capacitive load Cb ⎯ 400 pF
SCL, SDA falling time t
Sf
⎯ 300 ns