Datasheet

Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 925 of 980
REJ09B0050-0600
Item Symbol Min Typ Max Unit
Test
Conditions
Wait time after
SWE bit setting
*
1
x 1 — — μs
Wait time after
ESU bit setting
*
1
y 100 — — μs
Wait time after
E bit setting
*
1
*
6
z — — 10 ms
Erase time
wait
Wait time after
E bit clearing
*
1
α 10 — — μs
Erasing
Wait time after
ESU bit clearing
*
1
β 10 — — μs
Wait time after
EV bit setting
*
1
γ 20 — — μs
Wait time after
H'FF dummy
write
*
1
ε 2 — — μs
Wait time after
EV bit clearing
*
1
η 4 — — μs
Wait time after
SWE bit clearing
*
1
θ 100 — — μs
Maximum number
of erases
*
1
*
6
N — — 100 Times
Notes: 1. Follow the program/erase algorithms when making the time settings.
2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set
in flash memory control register 1 (FLMCR1). Does not include the program-verify
time.)
3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1.
Does not include the erase-verify time.)
4. Maximum programming time
t
P
(max) = Σ wait time after P bit setting (z)
N
i=1
5. The maximum number of writes (N) should be set as shown below according to the
actual set value of (z) so as not to exceed the maximum programming time (t
P
(max)).
The wait time after P bit setting (z) should be changed as follows according to the
number of writes (n).
Number of writes (n)
1 ≤ n ≤ 6 z = 30 µs
7 ≤ n ≤ 1000 z = 200 µs
(Additional programming)
Number of writes (n)
1 ≤ n ≤ 6 z = 10 µs
6. For the maximum erase time (t
E
(max)), the following relationship applies between the
wait time after E bit setting (z) and the maximum number of erases (N):
t
E
(max) = Wait time after E bit setting (z) × maximum number of erases (N)