Datasheet

Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 921 of 980
REJ09B0050-0600
(5) Timing of On-Chip Peripheral Modules
Table 25.22 Timing of On-Chip Peripheral Modules
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 8 MHz to 33 MHz, T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
I/O ports Output data delay time t
PWD
— 40 ns Figure 25.28
Input data setup time t
PRS
25 — ns
Input data hold time t
PRH
25 — ns
PPG Pulse output delay time t
POD
— 40 ns Figure 25.29
TPU Timer output delay time t
TOCD
— 40 ns Figure 25.30
Timer input setup time t
TICS
25 — ns
Timer clock input setup time t
TCKS
25 — ns Figure 25.31
Timer clock
pulse width
Single-edge
specification
t
TCKWH
1.5 — t
cyc
Both-edge
specification
t
TCKWL
2.5 — t
cyc
8-bit timer Timer output delay time t
TMOD
— 40 ns Figure 25.32
Timer reset input setup time t
TMRS
25 — ns Figure 25.34
Timer clock input setup time t
TMCS
25 — ns Figure 25.33
Timer clock
pulse width
Single-edge
specification
t
TMCWH
1.5 — t
cyc
Both-edge
specification
t
TMCWL
2.5 — t
cyc
WDT Overflow output delay time t
WOVD
— 40 ns Figure 25.35
SCI Asynchronous t
Scyc
4 — t
cyc
Figure 25.36
Input clock
cycle
Synchronous 6 —
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5
Transmit data delay time t
TXD
— 40 ns Figure 25.37
Receive data setup time
(synchronous)
t
RXS
40 — ns
Receive data hold time
(synchronous)
t
RXH
40 — ns
A/D
converter
Trigger input setup time t
TRGS
30 — ns Figure 25.38