Datasheet

Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 904 of 980
REJ09B0050-0600
φ
DREQ0, DREQ1
t
DRQS
t
DRQH
Figure 25.27 DMAC DREQ Input Timing
(5) Timing of On-Chip Peripheral Modules
Table 25.10 Timing of On-Chip Peripheral Modules
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 8 MHz to 33 MHz, T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
I/O ports Output data delay time t
PWD
— 40 ns Figure 25.28
Input data setup time t
PRS
25 — ns
Input data hold time t
PRH
25 — ns
PPG Pulse output delay time t
POD
— 40 ns Figure 25.29
TPU Timer output delay time t
TOCD
— 40 ns Figure 25.30
Timer input setup time t
TICS
25 — ns
Timer clock input setup time t
TCKS
25 — ns Figure 25.31
Timer clock
pulse width
Single-edge
specification
t
TCKWH
1.5 — t
cyc
Both-edge
specification
t
TCKWL
2.5 — t
cyc
8-bit timer Timer output delay time t
TMOD
— 40 ns Figure 25.32
Timer reset input setup time t
TMRS
25 — ns Figure 25.34
Timer clock input setup time t
TMCS
25 — ns Figure 25.33
Timer clock
pulse width
Single-edge
specification
t
TMCWH
1.5 — t
cyc
Both-edge
specification
t
TMCWL
2.5 — t
cyc