Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 902 of 980
REJ09B0050-0600
T
1
φ
A23 to A0
CS7 to CS0
AS
t
DACD1
t
DACD2
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
DACK0, DACK1
T
2
Figure 25.24 DMAC Single Address Transfer Timing: Two-State Access
