Datasheet

Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 897 of 980
REJ09B0050-0600
T
p
T
r
T
c1
T
c2
T
c3
T
c1
T
c2
T
c3
φ
A23 to A0
RAS3, RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
t
RCH
t
RCS2
t
AC8
t
CPW2
D15 to D0
AS
Read
Write
DACK timing: when DDS = 1
RAS timing: when RAST = 1
Notes:
DACK0, DACK1
Figure 25.17 DRAM Access Timing: Three-State Burst Access