Datasheet

Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 896 of 980
REJ09B0050-0600
T
p
t
AD
t
AD
t
AS2
t
AH2
t
CSD2
t
PCH1
t
AS3
t
CSD3
t
CASD1
t
AH3
t
CASD2
t
CASW2
t
AC2
t
AA5
t
AC7
t
WRD2
t
WDD
t
WDS2
t
WDH3
t
WCS2
t
WCH2
t
RDH2
t
OED2
t
OED1
φ
A23 to A0
RAS3, RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
D15 to D0
AS
T
r
T
c1
T
c2
T
c3
Write
Read
DACK timing: when DDS = 0
RAS timing: when RAST = 1
Notes:
DACK0, DACK1
t
DACD1
t
DACD2
t
WRD2
t
RDS2
Figure 25.16 DRAM Access Timing: Three-State Access (RAST = 1)