Datasheet

Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 895 of 980
REJ09B0050-0600
T
p
φ
A23 to A0
RAS3, RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
D15 to D0
AS
T
r
T
c1
t
CPW1
t
AC3
t
RCH
t
RCS1
T
c2
T
c1
T
c2
Read
Write
DACK timing: when DDS = 1
RAS timing: when RAST = 1
Notes:
DACK0, DACK1
t
DACD1
t
DACD2
Figure 25.15 DRAM Access Timing: Two-State Burst Access