Datasheet

Section 25 Electrical Characteristics
Rev.6.00 Mar. 18, 2009 Page 889 of 980
REJ09B0050-0600
T
h
t
AD
t
CSD1
t
AS1
t
ASD
t
AS3
t
RSD1
t
AC5
t
RDS1
t
RDH1
t
AH2
t
AH3
t
WDH3
t
WSW1
t
WDS2
t
WDD
t
AS3
t
WRD2
t
WRD2
t
RSD2
t
RSD1
t
AC2
t
RDS2
t
RDH2
t
AS3
t
RSD1
t
AH3
t
AH1
t
ASD
φ
A23 to A0
CS7 to CS0
AS
RD
D15 to D0
RD
D15 to D0
HWR, LWR
D15 to D0
T
1
T
2
T
t
Read
(RDNn = 1)
Read
(RDNn = 0)
Write
DACK0, DACK1
t
DACD1
t
DACD2
Figure 25.9 Basic Bus Timing: Two-State Access (CS Assertion Period Extended)