Datasheet

Section 2 CPU
Rev.6.00 Mar. 18, 2009 Page 31 of 980
REJ09B0050-0600
SP (ER7)
Free area
Stack area
Figure 2.8 Stack
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3 Extended Control Register (EXR)
EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC
instructions. When an instruction other than STC is executed, all interrupts including NMI are
masked in three states after the instruction is completed.
Bit Bit Name Initial Value R/W Description
7 T 0 R/W Trace Bit
When this bit is set to 1, trace exception processing
starts every when an instruction is executed. When
this bit is cleared to 0, instructions are consecutively
executed.
6 to
3
– All 1 – Reserved
These bits are always read as 1.
2 to 0 I2
I1
I0
1 R/W Interrupt Mask Bits 2 to 0
Specify interrupt request mask levels (0 to 7). For
details, see section 5, Interrupt Controller.