Datasheet

Section 24 List of Registers
Rev.6.00 Mar. 18, 2009 Page 840 of 980
REJ09B0050-0600
24.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbrevia-
tion Bit No. Address Module
Data
Width
Access
States
DTC mode register A MRA 8 H’BC00 DTC 16/32 2
DTC source address register SAR 24 DTC 16/32 2
DTC mode register B MRB 8 to DTC 16/32 2
DTC destination address register DAR 24 DTC 16/32 2
DTC transfer count register A CRA 16 DTC 16/32 2
DTC transfer count register B CRB 16 H’BFFF DTC 16/32 2
I
2
C bus control register A_0 ICCRA_0 8 H'FD58 IIC2_0 8 2
I
2
C bus control register B_0 ICCRB_0 8 H'FD59 IIC2_0 8 2
I
2
C bus mode register_0 ICMR_0 8 H'FD5A IIC2_0 8 2
I
2
C bus interrupt enable register_0 ICIER_0 8 H'FD5B IIC2_0 8 2
I
2
C bus status register_0 ICSR_0 8 H'FD5C IIC2_0 8 2
Slave address register_0 SAR_0 8 H'FD5D IIC2_0 8 2
I
2
C transfer data register_0 ICDRT_0 8 H'FD5E IIC2_0 8 2
I
2
C receive data register_0 ICDRR_0 8 H'FD5F IIC2_0 8 2
I
2
C bus control register A_1 ICCRA_1 8 H'FD60 IIC2_1 8 2
I
2
C bus control register B_1 ICCRB_1 8 H'FD61 IIC2_1 8 2
I
2
C bus mode register_1 ICMR_1 8 H'FD62 IIC2_1 8 2
I
2
C bus interrupt enable register_1 ICIER_1 8 H'FD63 IIC2_1 8 2
I
2
C bus status register_1 ICSR_1 8 H'FD64 IIC2_1 8 2
Slave address register_1 SAR_1 8 H'FD65 IIC2_1 8 2
I
2
C transfer data register_1 ICDRT_1 8 H'FD66 IIC2_1 8 2
I
2
C receive data register_1 ICDRR_1 8 H'FD67 IIC2_1 8 2
Serial expansion mode register_2 SEMR_2 8 H'FDA8 SCI_2 8 2
Interrupt priority register A IPRA 16 H'FE00 INT 16 2
Interrupt priority register B IPRB 16 H'FE02 INT 16 2
Interrupt priority register C IPRC 16 H'FE04 INT 16 2
Interrupt priority register D IPRD 16 H'FE06 INT 16 2