Datasheet

Section 24 List of Registers
Rev.6.00 Mar. 18, 2009 Page 839 of 980
REJ09B0050-0600
Section 24 List of Registers
The address list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
⎯ Registers are listed from the lower allocation addresses.
⎯ Registers are classified by functional modules.
⎯ The access size is indicated.
2. Register bits
⎯ Bit configurations of the registers are described in the same order as the register addresses.
⎯ Reserved bits are indicated by ⎯ in the bit name column.
⎯ No entry in the bit-name column indicates that the whole register is allocated as a counter
or for holding data.
⎯ For the registers of 16 or 32 bits, the MSB is described first.
3. Register states in each operating mode
⎯ Register states are described in the same order as the register addresses.
⎯ The register states described here are for the basic operating modes. If there is a specific
reset for an on-chip peripheral module, refer to the section on that on-chip peripheral
module.