Datasheet

Section 23 Power-Down Modes
Rev.6.00 Mar. 18, 2009 Page 838 of 980
REJ09B0050-0600
23.4.6 Notes on Clock Division Mode
The following points should be noted in clock division mode.
• Select the clock division ratio specified by the SCK2 to SCK0 bits so that the frequency of φ is
within the operation guaranteed range of clock cycle time (t
cyc
) shown in the Electrical
Characteristics. In other words, the range of φ must be specified to 8 MHz (min.); outside of
this range (φ < 8 MHz) must be prevented.
• All the on-chip peripheral modules operate on the φ. Therefore, note the time processing of
modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio.
• Note that the frequency of φ will be changed by changing the clock division ratio.