Datasheet

Section 23 Power-Down Modes
Rev.6.00 Mar. 18, 2009 Page 835 of 980
REJ09B0050-0600
Hardware Standby Mode Timing when Power Is Supplied (Only H8S/2368 0.18 μm F-ZTAT
Group): When entering hardware standby mode immediately after the power is supplied, the RES
signal must be driven low for a given period with retaining the STBY signal high. After the RES
signal is canceled, drive the STBY signal low.
(1) Power supply
RES
(2) Reset period
(3) Hardware standby mode
STBY
Figure 23.4 Hardware Standby Mode Timing when Power Is Supplied
23.2.5 Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR or EXMSTPCR is set to 1, module operation
stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues
operating independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI are retained.
After reset clearance, all modules other than the DMAC, and DTC are in module stop mode.
The module registers which are set in module stop mode cannot be read or written to.