Datasheet

Section 23 Power-Down Modes
Rev.6.00 Mar. 18, 2009 Page 834 of 980
REJ09B0050-0600
23.2.4 Hardware Standby Mode
Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made
to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this
LSI is in hardware standby mode.
Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the STBY
pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is
set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator
stabilizes (for details on the oscillation stabilization time, refer to table 23.2). When the RES pin is
subsequently driven high, a transition is made to the program execution state via the reset
exception handling state.
Hardware Standby Mode Timing: Figure 23.3 shows an example of hardware standby mode
timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,
waiting for the oscillation stabilization time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 23.3 Hardware Standby Mode Timing