Datasheet

Section 23 Power-Down Modes
Rev.6.00 Mar. 18, 2009 Page 828 of 980
REJ09B0050-0600
23.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
MSTPCR performs module stop mode control.
Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0
clears the module stop mode.
• MSTPCRH
Bit Bit Name Initial Value R/W Module
15 ACSE 0 R/W All-Module-Clocks-Stop Mode Enable
Enables or disables all-module-clocks-stop mode,
in which, when the CPU executes a SLEEP
instruction after module stop mode has been set
for all the on-chip peripheral functions controlled
by MSTPCR or the on-chip peripheral functions
except the TMR.
0: All-module-clocks-stop mode disabled
1: All-module-clocks-stop mode enabled
14 MSTP14 0 R/W ⎯
13 MSTP13 0 R/W DMA controller (DMAC)
12 MSTP12 0 R/W Data transfer controller (DTC)
11 MSTP11 1 R/W 16-bit timer-pulse unit (TPU)
10 MSTP10 1 R/W Programmable pulse generator (PPG)
9 MSTP9 1 R/W ⎯
8 MSTP8 1 R/W D/A converter (channels 2 and 3)
• MSTPCRL
Bit Bit Name Initial Value R/W Module
7 MSTP7 1 R/W ⎯
6 MSTP6 1 R/W A/D converter
5 MSTP5 1 R/W Serial communication interface 4 (SCI_4)
4 MSTP4 1 R/W Serial communication interface 3 (SCI_3)
3 MSTP3 1 R/W Serial communication interface 2 (SCI_2)
2 MSTP2 1 R/W Serial communication interface 1 (SCI_1)
1 MSTP1 1 R/W Serial communication interface 0 (SCI_0)
0 MSTP0 1 R/W 8-bit timer (TMR)