Datasheet

Section 23 Power-Down Modes
Rev.6.00 Mar. 18, 2009 Page 825 of 980
REJ09B0050-0600
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
1. The active or halted state can be selected by means of the MSTP0 bit in MSTPCR.
2. TDR, SSR, and RDR are halted (reset) and other registers are halted (retained).
3. BC2 to BC0 are halted (reset) and other registers are halted (retained).
Program-halted stateProgram execution state
High-speel mode
(Internal clock is PLL
circuit output clock)
Reset state
STBY pin = low
STBY pin = high
RES pin = low
SSBY = 0
MSTPCR =
H'FFFF (H'FFFE),
EXMSTPCR = H'FFFF,
SSBY = 0
SSBY = 1
SCK2 to
SCK0 ≠ 0
RES pin = high
SCK2 to
SCK0 = 0
SLEEP
instruction
Interrupt
*1
: Transition after exception handling : Power- down mode
SLEEP
instruction
Any interrupt
SLEEP
instruction
External
interrupt
*2
Notes: 1. NMI, IRQ0 to IRQ7, 8-bit timer interrupts, watchdog timer interrupts.
(8-bit timer interrupts are valid when MSTP0 = 0.)
2. NMI, IRQ0 to IRQ7
(IRQ0 to IRQ7 are valid when the corresponding bit in SSIER is 1.)
• From any state, a transition to hardware standby mode occurs when STBY is driven low.
• From any state except hardware standby mode, a transition to the reset state occurs when RES
is driven low.
Hardware
standby mode
Sleep mode
All
module-clocks-stop
mode
Software
standby mode
Clock division
mode
Figure 23.1 Mode Transitions