Datasheet

Section 22 Clock Pulse Generator
Rev.6.00 Mar. 18, 2009 Page 819 of 980
REJ09B0050-0600
2. A value is set in bits STS3 to STS0 to give the specified transition time.
3. The target value is set in bits STC1 and STC0, and a transition is made to software standby
mode.
4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
5. Software standby mode is cleared, and a transition time is secured in accordance with the
setting in STS3 to STS0.
6. After the set transition time has elapsed, this LSI resumes operation using the target
multiplication factor.
When STCS = 1, this LSI operates using the new multiplication factor immediately after bits
STC1 and STC0 are rewritten.
22.4 Frequency Divider
The frequency divider divides the PLL output clock to generate a 1/2 or 1/4 clock.
22.5 Usage Notes
22.5.1 Notes on Clock Pulse Generator
1. The following points should be noted since the frequency of φ changes according to the setting
of SCKCR and PLLCR.
Select the clock division ratio that is within the operation guaranteed range of clock cycle time
tcyc shown in the AC timing of Electrical Characteristics. In other words, the range of φ must
be specified from 8 MHz (min) to 33 MHz* (max); outside of this range must be prevented.
2. All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software
Standby Mode in section 23.2.3, Software Standby Mode, for details.
3. Note that the frequency of φ will be changed when setting SCKCR or PLLCR while executing
the external bus cycle with the write-data-buffer function.
Note: * 34 MHz for the H8S/2368 0.18μm F-ZTAT Group