Datasheet

Section 22 Clock Pulse Generator
Rev.6.00 Mar. 18, 2009 Page 814 of 980
REJ09B0050-0600
22.1.1 System Clock Control Register (SCKCR)
SCKCR controls φ clock output and selects operation when the frequency multiplication factor
used by the PLL circuit is changed, and the division ratio used by the divider.
Bit Bit Name Initial Value R/W Description
7 PSTOP 0 R/W φ Clock Output Disable
Controls φ output.
Normal Operation
0: φ output
1: Fixed high
Sleep Mode
0: φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
All module clock stop mode
0: φ output
1: Fixed high
6 — 0 R/W Reserved
Though this bit can be read from or written to, the
write value should always be 0.
5, 4 — All 0 — Reserved
These bits are always read as 0 and cannot be
modified.
3 STCS 0 R/W Frequency Multiplication Factor Switching Mode
Select
Selects the operation when the PLL circuit
frequency multiplication factor is changed.
0: Specified multiplication factor is valid after
transition to software standby mode
1: Specified multiplication factor is valid immediately
after STC1 and STC0 bits are rewritten