Datasheet

Section 22 Clock Pulse Generator

Rev.6.00 Mar. 18, 2009 Page 813 of 980

REJ09B0050-0600

Section 22 Clock Pulse Generator

This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and

internal clocks.

The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider.

Figure 22.1 shows a block diagram of the clock pulse generator.

EXTAL

PLL circuit

(×1, 2, 4)

Oscillator

Divider

System clock

to φ pin

Internal cloc

to peripheral

modules

SCK2 to SCK0

SCKCR

STC0, STC1

PLLCR

XTAL

Legend:

PLLCR: PLL system control register

SCKCR: System clock control register

Figure 22.1 Block Diagram of Clock Pulse Generator

The frequency can be changed by means of the PLL circuit. Frequency changes are made by

software by means of settings in the PLL control register (PLLCR) and the system clock control

22.1 Register Descriptions

The clock pulse generator has the following registers.

• System clock control register (SCKCR)

• PLL control register (PLLCR)

CPG0400A_010020020100